SN54ABT16543, SN74ABT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997
D
D
D
D
D
D
D
D
SN54ABT16543 . . . WD PACKAGE
SN74ABT16543 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16543 16-bit registered transceivers
contain two sets of D-type latches for temporary
storage of data flowing in either direction. The
’ABT16543 can be used as two 8-bit transceivers
or one 16-bit transceiver. Separate latch-enable
(LEAB or LEBA) and output-enable (OEAB or
OEBA) inputs are provided for each register to
permit independent control in either direction of
data flow.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
The A-to-B enable (CEAB) input must be low to
enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are
transparent; a subsequent low-to-high transition
of LEAB puts the A latches in the storage mode.
With CEAB and OEAB both low, the 3-state
B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to
A is similar but requires using the CEBA, LEBA,
and OEBA inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16543 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN54ABT16543, SN74ABT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997
FUNCTION TABLE†
(each 8-bit section)
INPUTS
CEAB
LEAB
OEAB
A
OUTPUT
B
H
X
X
X
Z
X
X
H
X
Z
L
H
L
X
L
L
L
L
B0‡
L
L
L
L
H
H
† A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-state input
conditions were established
2
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SN54ABT16543, SN74ABT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997
logic symbol†
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
56
54
55
1
3
2
29
31
30
28
26
27
2LEAB
1A1
1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
5
3
6D
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
6
2A3
2A4
2A5
2A6
2A7
2A8
4
52
51
8
49
9
48
10
47
12
45
13
44
14
43
15
9
12D
2A2
5D
16
11D
10
42
41
17
40
19
38
20
37
21
36
23
34
24
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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3
SN54ABT16543, SN74ABT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
56
54
55
1
3
2
C1
5
1D
52
1B1
C1
1D
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
29
31
30
28
26
27
C1
15
1D
C1
1D
To Seven Other Channels
4
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42
2B1
SN54ABT16543, SN74ABT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16543
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT16543
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
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–55
VCC
–24
V
V
0.8
0
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
85
°C
125
–40
5
SN54ABT16543, SN74ABT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
MIN
TA = 25°C
TYP†
MAX
SN54ABT16543
MIN
–1.2
MAX
SN74ABT16543
MIN
–1.2
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
V
V
IOL = 64 mA
0.55
0.55*
0.55
100
Control
inputs
UNIT
2
0.55
Vhys
MAX
V
mV
±1
±1
±1
±100
±100
±100
µ
µA
VCC = 5.5 V,,
VI = VCC or GND
IOZH‡
IOZL‡
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
50**
10
50
µA
–50**
–10
–50
µA
Ioff
VCC = 0,
VCC = 5.5 V,
VO = 5.5 V
VI or VO ≤ 4.5 V
±100
±100
µA
50
µA
VCC = 5.5 V,
VO = 2.5 V
Outputs high
–200
mA
II
A or B ports
ICEX
IO§
ICC
A or B ports
50
–50
–100
Outputs low
Control
inputs
–200
VI = 2.5 V or 0.5 V
50
–50
–200
–50
2
2
2
35
35
35
2
2
2
0.5
0.5
0.5
Outputs disabled
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
∆ICC¶
Ci
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
Outputs high
3
mA
mA
pF
Cio
A or B ports VO = 2.5 V or 0.5 V
8.5
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** These limits apply only to the SN74ABT16543.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN
tw
6
Pulse duration, LEAB or LEBA low
tsu
Set p time,
Setup
time data before LEAB↑ or LEBA↑
th
Hold time
time, data after LEAB↑ or LEBA↑
MAX
SN54ABT16543
MIN
MAX
SN74ABT16543
MIN
4
4
4
High
1.5
1.5
1.5
Low
3.5
3.5
3.5
High
1.5
1.5
1.5
Low
2
2
2
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UNIT
MAX
ns
ns
ns
SN54ABT16543, SN74ABT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT16543
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LE
A or B
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
tPZH
tPZL
CE
A or B
tPHZ
tPLZ
CE
A or B
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
MAX
0.8
2.5
3.3
0.8
3.9
0.9
2.7
4.4
0.9
5.2
1
3.1
4.3
1
5.3
1.2
3.3
4.8
1.2
5.7
0.8
3.4
4.3
0.8
5.3
1.1
3.8
7
1.1
7.9
1.9
4
6.3
1.9
7.2
1.6
3.3
4.6
1.6
5
0.9
3.8
4.9
0.9
6.3
1.2
4.2
6.8
1.2
7.9
2
4.5
6.4
2
7.3
1.7
3.9
5.1
1.7
5.6
UNIT
ns
ns
ns
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT16543
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LE
A or B
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
tPZH
tPZL
CE
A or B
tPHZ
tPLZ
CE
A or B
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• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
MAX
1
2.5
3.3
1
3.8
1
2.7
4.4
1
5.1
1
3.1
4.3
1
5.2
1.2
3.3
4.8
1.2
5.6
1
3.4
4.3
1
5.2
1.1
3.8
5.9
1.1
7
1.9
4
5
1.9
5.7
1.6
3.3
4.2
1.6
4.6
1
3.8
4.9
1
6.2
1.2
4.2
6.5
1.2
7.8
2
4.5
5.6
2
6.6
1.7
3.9
5.1
1.7
5.4
UNIT
ns
ns
ns
ns
ns
ns
7
SN54ABT16543, SN74ABT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
Output
3V
Output
Control
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9324101MXA
ACTIVE
CFP
WD
56
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9324101MX
A
SNJ54ABT16543W
D
SN74ABT16543DGGR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT16543
Samples
SN74ABT16543DL
ACTIVE
SSOP
DL
56
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT16543
Samples
SN74ABT16543DLR
ACTIVE
SSOP
DL
56
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT16543
Samples
SNJ54ABT16543WD
ACTIVE
CFP
WD
56
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9324101MX
A
SNJ54ABT16543W
D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of