SN74ABT16640DLR

SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 D D D D D D D D SN54ABT16640 . . . WD PACKAGE SN74ABT16640 . . . DGG OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus  Family State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL ) Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR description The ’ABT16640 are inverting 16-bit transceivers designed for asynchronous communication between data buses. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (1DIR and 2DIR) inputs. The output-enable (1OE and 2OE) inputs can be used to disable the device so that the buses are effectively isolated. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16640 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16640 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 logic symbol† 1OE 1DIR 48 1 25 2OE 2DIR 1A1 24 47 logic diagram (positive logic) 1OE G3 3 EN1 [BA] 3 EN2 [AB] G6 1DIR 1A3 1A4 1A5 1A6 1A7 1A8 2A1 1 2A3 2A4 2A5 2A6 2A7 2A8 2 1 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 1B1 2 46 1 1 2A2 1 6 EN4 [BA] 6 EN5 [AB] 1 1A2 48 1A1 14 33 16 32 17 30 19 29 20 27 22 26 23 2 1B1 1B3 1B4 To Seven Other Channels 1B5 1B6 1B7 2OE 25 1B8 2B1 5 35 47 1B2 2DIR 24 2B2 2B3 2B4 2B5 2B6 2A1 36 13 2B1 2B7 2B8 To Seven Other Channels † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16640 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16640 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 recommended operating conditions (see Note 3) SN54ABT16640 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate High-level input voltage SN74ABT16640 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Input voltage 0 Low-level output current Outputs enabled TA Operating free-air temperature NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 –55 VCC –24 V V 0.8 0 UNIT VCC –32 V V mA 48 64 mA 10 10 ns/V 85 °C 125 –40 3 SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN –1.2 MAX SN74ABT16640 MIN –1.2 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* IOL = 64 mA IOZH‡ IOZL‡ VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V Ioff VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V VCC = 5.5 V, VO = 2.5 V Outputs high ICEX IO§ 0.55 0.55* 0.55 A or B ports VCC = 5.5 V, IO = 0, VI = VCC or GND Outputs high ±1 ±1 ±1 ±100 ±100 ±100 50 50 50 µA –50 –50 µA ±100 µA 50 µA –180 mA –180 50 –40 –180 –50 2 2 2 32 32 32 Outputs disabled 2 2 2 1 1.5 1 0.05 0.05 0.05 Control inputs VCC = 5.5 V, Outputs enabled One input at 3.4 V,, Other inputs at Outputs disabled VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1.5 1.5 1.5 Control inputs VI = 2.5 V or 0.5 V ts Data inp inputs ∆ICC¶ Outputs low 3 Cio A or B ports VO = 2.5 V or 0.5 V 8 * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. POST OFFICE BOX 655303 µ µA –50 50 –100 V mV ±100 –50 V V 100 Control inputs UNIT 2 0.55 A or B ports 4 MAX –1.2 2.5 VI = VCC or GND Ci MIN 2.5 VCC = 5.5 V,, ICC SN54ABT16640 2.5 Vhys II TA = 25°C TYP† MAX • DALLAS, TEXAS 75265 mA mA pF pF SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT16640 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B tPHZ tPLZ OE A or B VCC = 5 V, TA = 25°C MIN MAX MIN TYP MAX 0.5 2.5 4.1 0.5 5.2 0.5 2.8 4 0.5 4.5 0.5 3.5 5.2 0.5 6.2 0.5 3.9 6 0.5 7.4 0.5 3.8 6.8 0.5 7.9 0.5 3 4.5 0.5 5 UNIT ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT16640 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B tPHZ tPLZ OE A or B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 5 V, TA = 25°C MIN TYP MAX MIN MAX 1 2.5 3.4 1 4.3 1.1 2.8 3.6 1.1 3.9 1.2 3.5 4.5 1.2 5.5 1.5 3.9 5 1.5 6.3 1.8 3.8 4.8 1.8 6.3 1.5 3 3.9 1.5 4.2 UNIT ns ns ns 5 SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL Output 3V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74ABT16640DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16640 SN74ABT16640DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16640 SN74ABT16640DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16640 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of