SN54ABT533, SN74ABT533A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186D – JANUARY 1991 – REVISED JANUARY 1997
D
D
D
D
SN54ABT533 . . . J OR W PACKAGE
SN74ABT533A . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
SN54ABT533 . . . FK PACKAGE
(TOP VIEW)
description
2D
2Q
3Q
3D
4D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
LE
5Q
5D
These octal transparent D-type latches with
3-state outputs are designed specifically for
driving
highly
capacitive
or
relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
8Q
D
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
1D
1Q
OE
VCC
D
When the latch-enable (LE) input is high, the
Q outputs follow the complements of the data
(D) inputs. When LE is taken low, the Q outputs
are latched at the inverse of the levels at the
D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operations of the latches. Previously stored data can be retained or new data
can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT533 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT533A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT533, SN74ABT533A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186D – JANUARY 1991 – REVISED JANUARY 1997
FUNCTION TABLE
(each latch)
INPUTS
LE
D
L
H
H
L
L
H
L
H
L
L
X
Q0
H
X
X
Z
logic symbol†
1
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
11
3
4
OUTPUT
Q
OE
logic diagram (positive logic)
OE
1
EN
LE
C1
1D
1
2
5
7
6
8
9
13
12
14
15
17
16
18
19
11
C1
1Q
1D
3
2
1Q
1D
2Q
3Q
4Q
To Seven Other Channels
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT533A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186D – JANUARY 1991 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT533
SN74ABT533A
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–24
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
85
°C
High-level input voltage
2
2
0.8
Input voltage
0
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
–55
125
V
0.8
0
–40
V
VCC
–32
V
V
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
Vhys
II
IOZH
IOZL
Ioff
ICEX
IO‡
ICC
∆ICC§
Ci
Co
VCC = 4
4.5
5V
MIN
TA = 25°C
TYP†
MAX
SN54ABT533
MIN
–1.2
MAX
SN74ABT533A
MIN
–1.2
MAX
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
V
0.55
0.55*
0.55
100
VI = VCC or GND
VO = 2.7 V
VCC = 5.5 V,
VCC = 0,
VO = 0.5 V
VI or VO ≤ 4.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VO = 5.5 V
VO = 2.5 V
5 5 V,
V IO = 0,
0
VCC = 5.5
VI = VCC or GND
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
V
mV
±1
±1
±1
µA
10
10
10
µA
–10
–10
–10
µA
±150
µA
50
µA
–180
mA
±150
Outputs high
50
–50
V
2
0.55
VCC = 5.5 V,
VCC = 5.5 V,
UNIT
50
–140
–180
Outputs high
1
250
–50
–180
250
–50
250
µA
Outputs low
24
30
30
30
mA
Outputs disabled
0.5
µA
250
250
250
Outputs high
1.5
1.5
1.5
Outputs low
1.5
1.5
1.5
1.5
1.5
1.5
Outputs disabled
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
mA
3.5
pF
6.5
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT533, SN74ABT533A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186D – JANUARY 1991 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT533
VCC = 5 V,
TA = 25°C
MIN
tw
tsu
Pulse duration, LE high
Setup time, data before LE↓
th
Hold time, data after LE↓
MIN
MAX
UNIT
MAX
3.3
3.3
ns
High or low
2.1
2.1
ns
High or low
1.5
1.5
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT533A
VCC = 5 V,
TA = 25°C
MIN
tw
tsu
Pulse duration, LE high
Setup time, data before LE↓
th
Hold time, data after LE↓
MIN
MAX
UNIT
MAX
3.3
3.3
ns
High or low
2.1
2.1
ns
High or low
2.1
2.1
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT533
PARAMETER
4
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
MAX
1.9
4.2
5.4
1.9
6.7
3.1
4.9
6.3
3.1
6.9
2.7
4.9
6.2
2.7
7.6
3.5
5.4
6.8
3.5
7.5
1.6
3.7
4.8
1.6
5.8
2.4
4.2
6.2
2.4
6.9
2.8
5.1
6.2
2.8
7.2
2
4.1
6
2
6.9
UNIT
ns
ns
ns
ns
SN54ABT533, SN74ABT533A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186D – JANUARY 1991 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT533A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
MAX
1.7
4.2
5.4
1.7
6.4
2.6
4.9
6.3
2.6
6.6
2.7
4.9
6.2
2.7
7.3
3.5
5.4
6.8
3.5
7.3
1.6
3.7
4.8
1.6
5.7
2.4
4.2
6.2
2.4
6.7
1.6
5.1
6.2
1.6
6.9
2
4.1
6
2
6.5
UNIT
ns
ns
ns
ns
5
SN54ABT533, SN74ABT533A
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186D – JANUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
Output
3V
Output
Control
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9584301Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629584301Q2A
SNJ54
ABT533FK
5962-9584301QRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9584301QR
A
SNJ54ABT533J
SN74ABT533AN
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74ABT533AN
Samples
SN74ABT533APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AB533A
Samples
SNJ54ABT533FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629584301Q2A
SNJ54
ABT533FK
SNJ54ABT533J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9584301QR
A
SNJ54ABT533J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of