SN54ABT540, SN74ABT540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS188C – FEBRUARY 1991 – REVISED JANUARY 1997
D
D
D
D
SN54ABT540 . . . J OR W PACKAGE
SN74ABT540 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54ABT540 . . . FK PACKAGE
(TOP VIEW)
description
The ’ABT540 octal buffers and line drivers are
ideal for driving bus lines or buffer memory
address registers. The devices feature inputs and
outputs on opposite sides of the package that
facilitate printed circuit board layout.
A3
A4
A5
A6
A7
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all corresponding
outputs are in the high-impedance state.
OE2
D
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
A2
A1
OE1
VCC
D
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT540 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT540 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE1
OE2
A
OUTPUT
Y
L
L
L
H
L
L
H
L
H
X
X
Z
X
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT540, SN74ABT540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS188C – FEBRUARY 1991 – REVISED JANUARY 1997
logic symbol†
1
OE1
logic diagram (positive logic)
OE1
&
19
EN
OE2
A1
A2
A3
A4
A5
A6
A7
A8
2
1
OE2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
Y1
A1
1
19
2
18
Y1
Y2
Y3
Y4
To Seven Other Channels
Y5
Y6
Y7
Y8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT540 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT540 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT540
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–24
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
5
5
ns/V
85
°C
High-level input voltage
2
2
0.8
Input voltage
0
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
SN74ABT540
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–55
125
0
–40
V
V
0.8
V
VCC
–32
V
mA
SN54ABT540, SN74ABT540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS188C – FEBRUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
Vhys
II
TA = 25°C
TYP†
MAX
SN54ABT540
MIN
–1.2
MAX
SN74ABT540
MIN
–1.2
MAX
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
Ioff
ICEX
IO‡
VI = VCC or GND
VO = 2.7 V
VCC = 5.5 V,
VCC = 0,
VO = 0.5 V
VI or VO ≤ 4.5 V
VCC = 5.5 V, VO = 5.5 V
VCC = 5.5 V,
Outputs high
VCC = 5.5
5 5 V,
V IO = 0,
0
VI = VCC or GND
ICC
VO = 2.5 V
Outputs high
0.55
0.55*
0.55
±1
µA
50
50
50
µA
–50
–50
–50
µA
±100
µA
±100
50
–100
–180
50
–50
–180
–50
50
µA
–180
mA
1
250
250
250
µA
24
30
30
30
mA
Outputs disabled
0.5
250
250
250
µA
Outputs enabled
1.5
1.5
1.5
Outputs disabled
0.05
0.05
0.05
1.5
1.5
1.5
Data
inputs
Control
inputs
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
Co
±1
Outputs low
VCC = 5.5 V,
One input at 3.4 V,,
Other inputs at
VCC or GND
Ci
V
mV
±1
–50
V
2
0.55
IOL = 64 mA
VCC = 5.5 V,
VCC = 5.5 V,
UNIT
V
100
IOZH
IOZL
∆ICC§
MIN
mA
3
pF
8
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABT540
MIN
TYP
MAX
MIN
1
2.9
4.1
1
3.1
4.3
1.1
3.4
1.1
MAX
SN74ABT540
MIN
MAX
1
1
4.8
1
1
4.8
4.9
1.1
1.1
5.9
3
5.8
1.1
1.1
6.4
1.5
5.3
6.8
1.5
1.5
7.3
1.2
4.4
5.7
1.2
1.2
6.2
UNIT
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT540, SN74ABT540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS188C – FEBRUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
Output
3V
Output
Control
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74ABT540DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AB540
Samples
SN74ABT540DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT540
Samples
SN74ABT540DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT540
Samples
SN74ABT540N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74ABT540N
Samples
SN74ABT540NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT540
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of