SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
•
•
•
•
•
•
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (– 32-mA IOH,
64-mA IOL )
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
SN54ABT646 . . . JT PACKAGE
SN74ABT646 . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
DIR
SAB
CLKAB
NC
VCC
CLKBA
SBA
A1
A2
A3
NC
A4
A5
A6
5
4 3 2
1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
19
11
12 13 14 15 16 17 18
OE
B1
B2
NC
B3
B4
B5
A7
A8
GND
NC
B8
B7
B6
Output-enable (OE) and direction-control (DIR)
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port may be stored in either
register or in both.
24
2
SN54ABT646 . . . FK PACKAGE
(TOP VIEW)
description
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ′ABT646.
1
NC – No internal connection
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT646 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT646 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74ABT646 is characterized for operation from – 40°C to 85°C.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
21
OE
L
3
DIR
L
23
1
CLKAB CLKBA
X
X
22
SBA
L
2
SAB
X
BUS B
BUS A
BUS A
BUS B
SCBS068E – JULY 1991 – REVISED JULY 1994
21
OE
L
1
23
CLKAB CLKBA
X
↑
X
↑
↑
↑
2
SAB
X
X
X
22
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
21
OE
L
L
22
SBA
X
BUS B
3
DIR
L
H
1
CLKAB
X
L
23
CLKBA
L
X
2
SAB
X
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
Pin numbers shown are for DB, DW, JT, NT, and PW packages.
2–2
2
SAB
L
BUS A
BUS B
BUS A
3
DIR
X
X
X
23
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
21
OE
X
X
H
1
CLKAB
X
3
DIR
H
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
22
SBA
H
X
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
FUNCTION TABLE
INPUTS
DATA I/Os
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1 THRU A8
X
X
↑
X
X
X
Input
B1 THRU B8
Unspecified†
Input
OPERATION OR FUNCTION
Store A, B unspecified†
Store B, A unspecified†
X
X
X
↑
X
X
Unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
† The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
logic symbol‡
21
OE
DIR
CLKBA
SBA
CLKAB
SAB
A1
3
23
22
1
2
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
≥1
4
1
5
6D
5
7
1
4D
5
A4
A5
A6
A7
A8
B1
1
≥1
2
7
19
A2
A3
20
6
18
7
17
8
16
9
15
10
14
11
13
B2
B3
B4
B5
B6
B7
B8
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and PW packages.
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• DALLAS, TEXAS 75265
2–3
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
logic diagram (positive logic)
OE
DIR
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight
Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, NT, and PW packages.
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
B1
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . – 0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.65 W
DW package . . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . . 1.3 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT646
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
– 24
Low-level output current
48
∆t /∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT646
MIN
2
2
0.8
Input voltage
0
5
TA
Operating free-air temperature
NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
– 55
125
– 40
V
V
0.8
0
UNIT
V
VCC
– 32
mA
V
64
mA
5
ns / V
85
°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = – 3 mA
VCC = 5 V,
VCC = 4
4.5
5V
SN54ABT646
MIN
–1.2
MAX
SN74ABT646
MIN
–1.2
2.5
IOH = – 3 mA
IOH = – 24 mA
3
3
3
2
2
IOH = – 32 mA
IOL = 48 mA
2*
VCC = 5.5 V,,
VI = VCC or GND
IOZH‡
IOZL‡
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
Ioff
ICEX
IO¶
VCC = 0,
VCC = 5.5 V,
VI or VO ≤ 4.5 V
VO = 5.5 V
Outputs high
VCC = 5.5 V,
VO = 2.5 V
IOL = 64 mA
0.55
V
±1
±1
±1
±100
10§
±100
50
±100
10§
– 10§
– 50
– 10§
µA
±100
µA
Control inputs
A or B ports
5 5 V,
V
0
VCC = 5.5
IO = 0,
VI = VCC or GND
V
V
0.55
0.55*
±100
50
– 50
UNIT
2
0.55
II
MAX
–1.2
2.5
VCC = 4
4.5
5V
–100
–180
50
– 50
–180
– 50
µA
µA
50
µA
–180
mA
Outputs high
250
250
250
µA
Outputs low
30
30
30
mA
250
250
250
µA
1.5
1.5
1.5
mA
Outputs disabled
∆ICC#
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
Cio
TA = 25°C
TYP†
MAX
2.5
VOL
ICC
MIN
Control inputs
A or B ports
7
pF
12
pF
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ This data sheet limit may vary among suppliers.
¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
VCC = 5 V,
TA = 25°C
fclock
tw
Clock frequency
Pulse duration, CLK high or low
tsu
Setup time,
time A or B before CLKAB↑ or CLKBA↑
th
Hold time, A or B after CLKAB↑ or CLKBA↑
POST OFFICE BOX 655303
SN74ABT646
MIN
MAX
MIN
MAX
MIN
MAX
0
125
0
125
0
125
4
4
4
High
3.5
3.5
3.5
Low
3
3
3
0
0
0
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2–6
SN54ABT646
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
TYP
SN54ABT646
MAX
125
CLKBA or CLKAB
A or B
A or B
B or A
SAB or SBA†
B or A
OE
A or B
OE
A or B
DIR
A or B
MIN
MAX
SN74ABT646
MIN
125
MHz
2.2
4
6.8
2.2
7.8
1.7
4
7.4
1.7
8.4
1.5
3
5.9
1.5
6.9
1.5
3.3
5.9
1.5
6.9
1.5
4
6.1
1.5
7.1
1.5
3.6
6.9
1.5
7.9
1
4.3
5.3
1
6.3
2.1
5.8
7.4
2.1
8.8
1.5
3.5
7.3
1.5
8.3
1.5
3
7
1.5
7.5
1.2
4.5
5.7
1.2
6.7
2.5
6.5
9
2.5
9.5
1.5
3.8
6.7
1.5
DIR
A or B
tPLZ
1.5
3.8
7.2
1.5
† These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
7.7
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
UNIT
MAX
8.2
ns
ns
ns
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–7
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT FOR OUTPUTS
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
(see Note B)
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note C)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
1.5 V
Output
Waveform 2
S1 at Open
(see Note C)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
2–8
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• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74ABT646DBR
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AB646
SN74ABT646DW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT646
SN74ABT646DWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT646
SN74ABT646PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AB646
SN74ABT646PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AB646
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of