SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
D
D
D
D
D
D
D
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
High-Drive Outputs (–32-mA IOH,
64-mA IOL )
Multiplexed Real-Time and Stored Data
Inverting Data Paths
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
SN54ABT651 . . . JT PACKAGE
SN74ABT651 . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
SN54ABT651 . . . FK PACKAGE
(TOP VIEW)
description
A1
A2
A3
NC
A4
A5
A6
5
4
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
19
11
12 13 14 15 16 17 18
OEBA
B1
B2
NC
B3
B4
B5
A7
A8
GND
NC
B8
B7
B6
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. The
select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. A low input level selects real-time
data, and a high input level selects stored data.
Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the ’ABT651 devices.
1
OEAB
SAB
CLKAB
NC
VCC
CLKBA
SAB
D
NC – No internal connection
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all
the other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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1
SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
description (continued)
The SN54ABT651 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT651 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
Input
Store A and B data
X
H
↑
H or L
X
Input
Unspecified†
Store A, hold B
H
H
↑
↑
X
X‡
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
Unspecified†
Input
Hold A, store B
L
L
↑
↑
X
X
X‡
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
† The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡ When select control is low, clocks can occur simultaneously if allowances are made for propagation delays from A to B (B to A) plus setup and
hold times. When select control is high, clocks must be staggered to load both registers.
2
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• DALLAS, TEXAS 75265
SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
1
23
2
CLKAB CLKBA SAB
X
X
X
22
SBA
L
21
OEBA
H
X
H
1
23
2
CLKAB CLKBA SAB
↑
X
↑
X
↑
↑
23
CLKBA
X
2
SAB
L
X
X
X
BUS A
BUS A
3
1
CLKAB
X
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
OEAB
X
L
L
BUS B
3
21
OEAB OEBA
H
H
BUS B
3
21
OEAB OEBA
L
L
BUS A
BUS A
BUS B
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
22
3
21
1
23
2
22
SBA
OEAB
H
OEBA
L
CLKAB
CLKBA
SAB
SBA
H or L
H or L
H
H
X
X
X
TRANSFER STORED DATA TO A AND/OR B
STORAGE FROM A, B, OR A AND B
Pin numbers are for the DB, DW, JT, NT, and PW packages.
Figure 1. Bus-Management Functions
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3
SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
logic symbol†
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
A1
21
3
23
22
1
EN1 [BA]
EN2 [AB]
C4
G5
2
C6
G7
4
≥1
1
7
1
A3
A4
A5
A6
A7
A8
4D
≥1
B1
2
7
5
19
6
18
7
17
8
16
9
15
10
14
11
13
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and PW packages.
4
20
5 1
6D
A2
5
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B2
B3
B4
B5
B6
B7
B8
SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
logic diagram (positive logic)
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight Channels
1D
C1
4
A1
20
1D
B1
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, NT, and PW packages.
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5
SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT651 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT651 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions (see Note 3)
SN54ABT651
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–24
Low-level output current
∆t/∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT651
MIN
2
2
0.8
Input voltage
0
UNIT
V
V
0.8
V
VCC
–32
V
mA
48
64
mA
5
5
ns/V
0
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused pins (control or I/O) of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303
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SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
MIN
SN54ABT651
MIN
–1.2
MAX
SN74ABT651
MIN
–1.2
MAX
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
VCC = 5
5.5
5V
V,
VI = VCC or GND
IOZH‡
IOZL‡
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
Ioff
VCC = 0,
VCC = 5.5 V,
VO = 5.5 V
VI or VO ≤ 4.5 V
IO§
VCC = 5.5 V,
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
VO = 2.5 V
Outputs high
A or B ports
ICEX
0.55
0.55*
0.55
mV
±1
±1
±100
±100
±100
50
50
50
µA
–50
–50
Outputs high
50
–100
–180
Outputs low
Outputs disabled
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
∆ICC¶
Ci
Control inputs
Cio
A or B ports
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
V
±1
±100
–50
V
V
100
Control inputs
UNIT
2
0.55
Vhys
II
TA = 25°C
TYP†
MAX
50
–50
–180
–50
µA
–50
µA
±100
µA
50
µA
–180
mA
250
250
250
µA
30
30
30
mA
250
250
250
µA
1.5
1.5
1.5
mA
6
pF
7.5
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
VCC = 5 V,
TA = 25°C
MIN
MAX
SN54ABT651
MIN
125
MAX
SN74ABT651
MIN
125
UNIT
MAX
fclock
tw
Clock frequency
Pulse duration, CLK high or low
4
4
4
125
MHz
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
3
3
3
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
0
0
0
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
TYP
SN54ABT651
MAX
125
CLKBA or CLKAB
A or B
A or B
B or A
SAB or SBA†
A or B
OEBA
A
OEBA
A
OEAB
B
MIN
MAX
125
MHz
4
5.1
2.2
5.9
2.2
5.6
1.7
4
5.1
1.7
5.9
1.7
5.6
1.5
4
5.1
1.5
6.4
1.5
6.2
1.5
3.3
4.6
1.5
5.6
1.5
5.4
1.5
4
5.1
1.5
6.8
1.5
6.5
1.5
3.6
4.9
1.5
6.2
1.5
5.9
1.3
3.6
4.6
1.3
5.9
1.3
5.8
2.5
5.7
6.8
2.5
8.9
2.5
8.5
1.5
3.2
4.5
1.5
6.2
1.5
5
1.5
3
3.8
1.5
4.3
1.5
4.1
1.8
4.3
6.1
1.8
6.7
1.8
6.5
2.9
5.5
6.5
2.9
7.6
2.9
7.4
1.5
5.5
1.5
5.1
• DALLAS, TEXAS 75265
UNIT
MAX
2.2
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
MIN
125
1.5
3.3
4.5
1.5
6.5
OEAB
B
tPLZ
1.5
3.4
4.4
1.5
5.2
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
8
SN74ABT651
ns
ns
ns
ns
ns
ns
ns
SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
1.5 V
th
3V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74ABT651DW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT651
SN74ABT651DWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT651
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of