SN74ABT821ANSRG4

SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193E – FEBRUARY 1991 – REVISED MAY 1997 D D D D D D State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs SN54ABT821 . . . JT OR W PACKAGE SN74ABT821A . . . DB, DW, OR NT PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK SN54ABT821 . . . FK PACKAGE (TOP VIEW) The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the devices provide true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. 4 3D 4D 5D NC 6D 7D 8D 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 3Q 4Q 5Q NC 6Q 7Q 8Q 9D 10D GND NC CLK 10Q 9Q These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. 2D 1D description OE NC VCC 1Q 2Q D NC – No internal connection OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT821 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT821A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193E – FEBRUARY 1991 – REVISED MAY 1997 FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic symbol† OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 EN 13 C2 2 23 2D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, and W packages. logic diagram (positive logic) OE CLK 1 13 C1 1D 2 1D To Nine Other Channels Pin numbers shown are for the DB, DW, JT, NT, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 1Q SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193E – FEBRUARY 1991 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT821A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54ABT821 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current 48 ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage SN74ABT821A MIN 2 2 0.8 Input voltage 0 10 mA 64 mA 10 –40 V VCC –32 V ns/V µs/V 200 125 V V 0.8 0 UNIT 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193E – FEBRUARY 1991 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL Vhys II IOZPU‡ IOZPD‡ IOZH IOZL Ioff ICEX IO§ VCC = 4 4.5 5V SN54ABT821 MIN –1.2 MAX SN74ABT821A MIN –1.2 MAX –1.2 2.5 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* UNIT V V 2 0.55 IOL = 64 mA 0.55 0.55* 0.55 100 V mV ±1 ±1 ±1 µA ±50* ±50 µA VCC = 2.1 V to 0, VO = 0.5 to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V ±50* ±50 µA 10 10 10 µA VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V VCC = 0, VI or VO ≤ 4.5 V –10 –10 –10 µA ±100 µA VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, ±100 Outputs high 50 VO = 2.5 V Outputs high –50 –100 –180 50 –50 –180 –50 50 µA –180 mA 1 250 250 250 µA Outputs low 24 38 38 38 mA Outputs disabled 0.5 250 250 250 µA 1.5 1.5 1.5 mA ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Co TA = 25°C TYP† MAX VCC = 0 to 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 to 2.7 V, OE = X VCC = 5.5 5 5 V, V IO = 0, 0 VI = VCC or GND ICC MIN 3.5 pF 7.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ This parameter is characterized, but not production tested. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C fclock 4 Clock frequency MIN MAX 0 125 SN54ABT821 MIN MAX 0 125 SN74ABT821A MIN MAX 0 125 High 2.9 2.9 2.9 Low 3.8 3.8 3.8 UNIT MHz tw Pulse duration duration, CLK high or low tsu th Setup time, data before CLK↑ 2.1 2.1 2.1 ns Hold time, data after CLK↑ 1.3 1.3 1.3 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193E – FEBRUARY 1991 – REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT821 PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) CLK Q OE Q OE Q VCC = 5 V, TA = 25°C MIN TYP MAX 125 1.6† 2.1† 4.1 5.6 4.6 6.2 MIN MAX 125 1.6† 2.1† 6.9 UNIT MHz 6.9 1 3 4.5 1 6 2.2 4.1 5.6 2.2 6.5 2.7 1.7† 4.7 6.2 7 4.6 6.1 2.7 1.7† 7 ns ns ns † This data sheet limit may vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT821A PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) CLK Q OE Q OE Q VCC = 5 V, TA = 25°C MIN TYP MAX 125 1.6† 4.1 5.6 2.3† 4.6 6.2 MIN MAX 125 1.6† 2.3† 6.2 UNIT MHz 6.7 1 3 4.5 1 5.8 2.2 4.1 5.6 2.2 6.3 2.7 1.7† 4.7 6.2 6.1 2.7 1.7† 6.7 4.6 6.5 ns ns ns † This data sheet limit may vary among suppliers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193E – FEBRUARY 1991 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V tPHL tPLH VOH 1.5 V Output 1.5 V VOL 1.5 V 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ VOH Output 3V Output Control tPLH tPHL 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at Open (see Note B) tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9469101QLA ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9469101QL A SNJ54ABT821JT SN74ABT821ADW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT821A Samples SN74ABT821ADWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT821A Samples SNJ54ABT821JT ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9469101QL A SNJ54ABT821JT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of