SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
D
D
D
D
D
D
SN54ABT833 . . . JT PACKAGE
SN74ABT833 . . . DW OR NT PACKAGE
(TOP VIEW)
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
A 9-bit parity generator/checker generates a
parity-odd (PARITY) output and monitors the
parity of the I/O ports with the ERR flag. ERR is
clocked into the register on the rising edge of the
clock (CLK) input. The error flag register is cleared
with a low pulse on the clear (CLR) input. When
both OEA and OEB are low, data is transferred
from the A bus to the B bus and inverted parity is
generated. Inverted parity is a forced error
condition that gives the designer more system
diagnostic capability.
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
CLK
SN54ABT833 . . . FK PACKAGE
(TOP VIEW)
description
4
A3
A4
A5
NC
A6
A7
A8
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
B3
B4
B5
NC
B6
B7
B8
ERR
CLR
GND
NC
CLK
OEB
PARITY
The ’ABT833 8-bit to 9-bit parity transceivers are
designed for communication between data buses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR) output indicates whether or not
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT833 provide true
data at their outputs.
1
OEA
NC
V CC
B1
B2
D
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
High-Drive Outputs (–32-mA IOH,
64-mA IOL )
Parity Error Flag With Parity
Generator/Checker
Register for Storage of the Parity Error Flag
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
A2
A1
D
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
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1
SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT833 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT833 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT AND I/O
Ai
Σ OF H’s
OEB
OEA
CLR
CLK
L
H
X
X
H
L
H
↑
NA
X
X
L
X
X
H
No↑
X
L
No↑
X
H
↑
Odd
H
↑
Even
H
L
H
L
X
Bi†
Σ OF H’s
A
B
NA
NA
A
B
NA
NA
X
NA
NA
Odd
Even
Odd
Even
X
L
H
FUNCTION
ERR‡
A data to B bus and
generate parity
NA
H
L
B data to A bus and
check parity
H
Check error-flag register
NC
X
Z
Z
Z
H
Isolation§
H
L
Odd
X
PARITY
NA
Even
NA
H
A
L
A data to B bus and
generate inverted parity
NA
NA = not applicable, NC = no change, X = don’t care
† Summation of high-level inputs includes PARITY along with Bi inputs.
‡ Output states shown assume ERR was previously high.
§ In this mode, ERR (when clocked) shows inverted parity of the A bus.
logic symbol¶
CLK
CLR
OEA
OEB
A1
A2
A3
A4
A5
A6
A7
A8
13
11
1
14
2
CLK
Φ
10
ERR
CLR
OEA
OEB
PARITY
1
1
23
22
4
21
5
20
6
A Bus
19
B Bus
7
18
8
17
8
8
¶ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
15
3
9
ERR
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16
PARITY
B1
B2
B3
B4
B5
B6
B7
B8
SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
logic diagram (positive logic)
A1–A8
2–9
8x
8
16–23
8
B1–B8
EN
8x
8
EN
OEB
14
15
OEA
1
8
PARITY
8
1 MUX
1
2k
9
1
P
1
G1
1D
CLK
CLR
13
10 ERR
C1
11
R
Pin numbers shown are for the DW, JT, and NT packages.
ERROR-FLAG FUNCTION TABLE
CLR
CLK
POINT P
OUTPUT
PRE-STATE
ERRn–1†
H
↑
H
H
H
↑
X
L
L
H
↑
L
X
L
INPUTS
INTERNAL
TO DEVICE
OUTPUT
ERR
H
FUNCTION
Sample
L
X
X
X
H
Clear
† The state of ERR before any changes at CLR, CLK, or point P
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3
SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
error-flag waveforms
H
OEB
L
H
OEA
L
Even
Bi + PARITY
Odd
tsu
th
H
CLK
L
tw
tsu
tw
H
CLR
L
tPHL
tPLH
H
ERR
L
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT833 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT833 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
4
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SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT833
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
VOH
IOH
High-level output voltage
ERR
High-level output current
Except ERR
IOL
∆t/∆v
Low-level output current
High-level input voltage
SN74ABT833
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Input transition rise or fall rate
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
–55
UNIT
V
V
0.8
V
VCC
5.5
V
–24
–32
mA
48
64
mA
5
5
ns/V
85
°C
VCC
5.5
125
0
–40
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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5
SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
All outputs
except ERR
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
Vhys
IOH
VCC = 4
4.5
5V
MIN
TA = 25°C
TYP†
MAX
SN54ABT833
MIN
–1.2
MAX
SN74ABT833
MIN
–1.2
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 24 mA
2*
2
0.55
IOL = 64 mA
VCC = 4.5 V,
VOH = 5.5 V
VCC = 5
5.5
5V
V,
VI = VCC or GND
VCC = 0,
VCC = 5.5 V,
V
V
0.55
0.55*
0.55
100
ERR
UNIT
V
mV
20
20
20
µA
±1
±1
±1
±100
±100
±100
VI = GND
VO = 2.7 V
–50
–50
–50
µA
50
50
50
µA
VCC = 5.5 V,
VCC = 0,
VO = 0.5 V
VI or VO ≤ 4.5 V
–50
–50
–50
µA
±100
µA
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
IO§
VCC = 5.5 V,
II
IIL
IOZH‡
IOZL‡
Control inputs
A or B ports
A or B ports
Ioff
ICC
A or B ports
Data inp
inputs
ts
∆ICC#
Control inputs
Ci
Control inputs
Cio
A or B ports
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
VO = 2.5 V
Outputs high
±100
–50
µA
50
50
50
µA
–100 –200¶
–50 –200¶
–50 –200¶
mA
1
µA
Outputs low
24
250
38¶
250
38¶
250
38¶
mA
Outputs disabled
0.5
250
250
250
µA
1.5
1.5
1.5
mA
50
50
50
µA
1.5
1.5
1.5
mA
VCC = 5.5 V,
Outputs enabled
One input at 3.4 V,,
Other inputs at
Outputs disabled
VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
4.5
pF
10.5
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ These limits may vary among suppliers.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
MAX
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SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time after CLK↑
MAX
SN54ABT833
MIN
MAX
SN74ABT833
MIN
CLK high or low
3
3
3
CLR low
3
3
3
B or PARITY high
9.8
9.8
9.8
B or PARITY low
8.1
8.1
8.1
CLR
2
2
2
B or PARITY
0
0
0
UNIT
MAX
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
A
PARITY
tPZH
tPZL
OE
PARAMETER
tPLH
tPHL
CLR
CLK
VCC = 5 V,
TA = 25°C
MIN TYP†
MAX
SN54ABT833
SN74ABT833
MIN
MAX
MIN
MAX
1.2
5.4
1.2
1
5.4
1
5.3
5.3‡
1.2
2.8
1
3
4.8
4.8‡
2.1
5.5
9.5
2.1
11.3
2.1
11.2
2.5
5.3
9.7
2.5
11.1
2.5
11
PARITY
2.6
2.6‡
6.2
8.5
2.6
2.6‡
10.5
ERR
1
1.2‡
3.2
8.6
4.8‡
2.6
2.6‡
10.6
5.8
5.3
5.7
1
1.2‡
5.2
2.8
1
‡
1.2
6.6
1
1.3‡
6.5‡
6.5‡
1.9‡
2.2‡
7.9
8.2
tPZH
tPZL
A B,
A,
B or PARITY
1
1.3‡
3.7
5.8‡
OE
3.8
5.8
tPHZ
tPLZ
OE
A B,
A,
B or PARITY
1.9‡
2.2‡
4.4
7.3
1
‡
1.3
1.9‡
4.4
7.7
2.2‡
10.1
6.3
6.6
8
10
6.2
8.1
UNIT
ns
ns
ns
ns
ns
ns
† All typical values are at VCC = 5 V.
‡ These limits may vary among suppliers.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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7
SN54ABT833, SN74ABT833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
500 Ω
ERR
S1
tPHL
tPLH
7V
7V
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
1.5 V
th
3V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74ABT833DW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT833
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of