SN74ABTH25245DWG4

SN54ABTH25245, SN74ABTH25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS251F – JUNE 1992 – REVISED MAY 1997 D D D D D D D description The ’ABTH25245 are 25-Ω octal bus transceivers designed for asynchronous communication between data buses. They improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers. These devices allow noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can disable the device so that both buses are effectively isolated. When OE is low, the device is active. SN54ABTH25245 . . . JT PACKAGE SN74ABTH25245 . . . DW OR NT PACKAGE (TOP VIEW) A1 GND A2 A3 GND A4 A5 GND A6 A7 GND A8 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DIR B1 B2 VCC B3 B4 B5 B6 VCC B7 B8 OE SN54ABTH25245 . . . FK PACKAGE (TOP VIEW) B4 B5 B6 NC VCC B7 B8 D State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Designed to Facilitate Incident-Wave Switching for Line Impedances of 25 Ω or Greater Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) DIPs B3 5 4 3 2 1 28 27 26 25 VCC B2 NC B1 DIR A1 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 OE A8 GND NC A7 A6 GND GND A2 A3 NC GND A4 A5 D NC – No internal connection These transceivers are capable of sinking 188 mA of IOL current, which facilitates switching 25-Ω transmission lines on the incident wave. The distributed VCC and GND pins minimize switching noise for more-reliable system operation. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABTH25245, SN74ABTH25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS251F – JUNE 1992 – REVISED MAY 1997 description (continued) When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABTH25245 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABTH25245 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation logic symbol† OE DIR A1 13 24 1 G3 3 EN1 [BA] 3 EN2 [AB] 23 1 B1 2 A2 A3 A4 A5 A6 A7 A8 3 22 4 20 6 19 7 18 9 17 10 15 12 14 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B2 B3 B4 B5 B6 B7 B8 SN54ABTH25245, SN74ABTH25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS251F – JUNE 1992 – REVISED MAY 1997 logic diagram (positive logic) DIR 24 13 A1 OE 1 23 B1 To Seven Other Channels Pin numbers shown are for the DW, JT, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Current into any output in the low state, IO: SN74ABTH25245 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . 376 mA SN74ABTH25245 (B port) . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABTH25245, SN74ABTH25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS251F – JUNE 1992 – REVISED MAY 1997 recommended operating conditions (see Note 3) SN54ABTH25245 MIN MAX 4.5 5.5 4.5 5.5 Supply voltage VIL VI Low-level input voltage IIK Input clamp current IOH High level output current High-level IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 2 2 0.8 Input voltage 0 Outputs enabled 0.8 0 VCC –18 –80 –80 B port –32 –32 A port 188 188 B port 64 64 4 4 10 10 Control inputs A or B ports PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 VCC –18 • DALLAS, TEXAS 75265 –40 V V V mA mA mA ns/V µs/V 200 125 UNIT V A port NOTE 3: Unused control pins must be held high or low to prevent them from floating. 4 MAX VCC VIH High-level input voltage SN74ABTH25245 MIN 85 °C SN54ABTH25245, SN74ABTH25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS251F – JUNE 1992 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.75 V, II = –18 mA IOH = –3 mA VCC = 4.5 V, VCC = 4.5 V, MIN –1.2 IOH = –80 mA IOH = –3 mA 2.4 2.4 2.5 2.5 VCC = 5 V, VCC = 4.5 V, IOH = –3 mA IOH = –32 mA 3 3 2* 2 A port VCC = 4 4.5 5V IOL = 94 mA IOL = 188 mA 0.55 0.7 0.7 B port VCC = 4.5 V, IOL = 64 mA 0.55* 0.55 Control inputs A or B ports VCC = 0 to 5.5 V, VCC = 2.1 V to 5.5 V, VI = VCC or GND VI = VCC or GND A or B ports 5V VCC = 4 4.5 VI = 0.8 V VI = 2 V B port Vhys II(hold) I(h ld) –1.2 2.7 VOH II SN74ABTH25245 TYP† MAX MIN 2.7 A port VOL SN54ABTH25245 TYP† MAX TEST CONDITIONS UNIT V V 0.55 100 100 mV ±1 ±1 ± 20 ± 20 100 100 –100 –100 V µA µA IOZPU‡ IOZPD‡ VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA Ioff ICEX IO§ VCC = 0, VCC = 5.5 V, VI or VO ≤ 4.5 V VO = 5.5 V ±100 ±100 µA 50 50 µA VCC = 5.5 V, VO = 2.5 V Outputs high –210 mA B port ICC VCC = 5.5 V, Outputs open, VI = VCC or GND ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci Control inputs VCC = 5 V, VCC = 5 V, –50 –210 Outputs low Outputs disabled VI = VCC or GND VO = VCC or GND 4 –50 500 500 µA 20 20 mA 500 500 µA 1 1 mA 4 pF Cio A or B ports 11.5 11.5 * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter is characterized, but not production tested. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABTH25245, SN74ABTH25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS251F – JUNE 1992 – REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B tPHZ tPLZ OE A or B PARAMETER VCC = 5 V, TA = 25°C SN54ABTH25245 MIN TYP MAX MIN 1 2.3 3.5 1 2.4 1.5 1.4 MIN MAX 1 1 3.9 3.5 1 1 4.3 3.7 5.4 1.5 1.5 6.5 4 5.8 1.4 1.4 6.8 2 4.3 6.1 2 2 7.2 2 3.9 5.8 2 2 6.4 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX SN74ABTH25245 UNIT ns ns ns SN54ABTH25245, SN74ABTH25245 25-Ω OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS251F – JUNE 1992 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device SN74ABTH25245DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABTH25245DWR SOIC DW 24 2000 350.0 350.0 43.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) SN74ABTH25245DW DW SOIC 24 25 506.98 12.7 4826 6.6 Pack Materials-Page 3 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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