SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MAY 1997
D
D
D
D
D
Members of the Texas Instruments
Widebus+ Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
UBE (Universal Bus Exchanger)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D
D
D
D
D
High-Impedance State During Power Up
and Power Down
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include 80-Pin Plastic
Thin Quad Flat (PN) Package With
12 × 12-mm Body Using 0.5-mm Lead Pitch
and 84-Pin Ceramic Quad Flat (HT) Package
C11
C10
C9
A1
SELA
OEA
OEC
SELC
LEC
CLKC
C18
C17
VCC
GND
C16
C15
C14
C13
C12
GND
SN74ABTH32318 . . . PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
A2
A3
A4
GND
A5
A6
A7
A8
A9
VCC
GND
A10
A11
A12
A13
A14
GND
A15
A16
A17
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
41
20
C8
C7
C6
GND
C5
C4
C3
C2
C1
VCC
GND
B18
B17
B16
B15
B14
GND
B13
B12
B11
A18
CLKA
LEA
OEB
SELB
LEB
CLKB
B1
B2
VCC
GND
B3
B4
B5
B6
B7
GND
B8
B9
B10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC-ΙΙB, and UBE are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MAY 1997
GND
C11
C10
C9
A1
SELA
OEA
OEC
SELC
LEC
CLKC
C18
C17
VCC
NC
GND
C16
C15
C14
C13
C12
SN54ABTH32318 . . . HT PACKAGE
(TOP VIEW)
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
A2
A3
A4
GND
A5
A6
A7
A8
A9
VCC
NC
GND
A10
A11
A12
A13
A14
GND
A15
A16
A17
1
63
2
62
3
61
4
60
5
59
6
58
7
57
8
56
9
55
10
54
11
53
12
52
13
51
14
50
15
49
16
48
17
47
18
46
19
45
20
44
43
21
C8
C7
C6
GND
C5
C4
C3
C2
C1
VCC
NC
GND
B18
B17
B16
B15
B14
GND
B13
B12
B11
B10
NC
GND
B3
B4
B5
B6
B7
GND
B8
B9
A18
CLKA
LEA
OEB
SELB
LEB
CLKB
B1
B2
VCC
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
NC – No internal connection
description
The ’ABTH32318 consist of three 18-bit registered input/output (I/O) ports. These registers combine D-type
latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be
exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations
of real-time and stored data can be exchanged among the three ports.
Data flow in each direction is controlled by the output-enable (OEA, OEB, and OEC), select-control (SELA,
SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data
register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held
at a high or low logic level. If LEA is low, data is stored on the low-to-high transition of CLKA. Output data
selection is accomplished by the select-control pins. All three ports have active-low output enables, so when
the output-enable input is low, the outputs are active; when the output-enable input is high, the outputs are in
the high-impedance state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MAY 1997
description (continued)
The SN54ABTH32318 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32318 is characterized for operation from –40°C to 85°C.
Function Tables
STORAGE†
INPUTS
A
OUTPUT
CLKA
LEA
↑
L
L
L
↑
L
H
H
H
L
X
L
L
X
Q0‡
Q0‡
X
H
L
L
X
H
H
H
† A-port register shown. B and C ports are
similar but use CLKB, CLKC, LEB, and
LEC.
‡ Output level before the indicated
steady-state input conditions were
established
A-PORT OUTPUT
INPUTS
OEA
OUTPUT A
SELA
H
X
Z
L
H
Output of C register
L
L
Output of B register
B-PORT OUTPUT
INPUTS
OUTPUT B
OEB
SELB
H
X
L
H
Output of A register
L
L
Output of C register
Z
C-PORT OUTPUT
INPUTS
OEC
OUTPUT C
SELC
H
X
Z
L
H
Output of B register
L
L
Output of A register
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MAY 1997
logic diagram (positive logic)
OEC
SELC
CLKC
LEC
C1
OEB
SELB
CLKB
LEB
B1
OEA
SELA
CLKA
LEA
A1
77
76
Q
CLK
74
75
LE
D
52
24
25
Q
CLK
27
26
LE
D
28
78
79
Q
CLK
22
23
LE
D
80
1 of 18 Channels
Pin numbers shown are for the PN package.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABTH32318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABTH32318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): PN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH32318
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
High-level input voltage
SN74ABTH32318
MIN
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
VCC
–24
V
V
0.8
0
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
µs/V
200
125
–40
85
°C
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
II = –18 mA
IOH = –3 mA
VCC = 5 V,
IOH = –3 mA
IOH = –24 mA
VCC = 4
4.5
5V
II(h
ld)
I(hold)
–1.2
–1.2
2.5
3
3
0.55
0.55
IOL = 64 mA
0.55
0.55
A, B, or C ports
VCC = 0 to 5.5 V,
VCC = 2.1 V to 5.5 V,
VI = VCC or GND
VI = VCC or GND
A B
A,
B, or C ports
VCC = 4
4.5
5V
VI = 0.8 V
VI = 2 V
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X
Ioff
ICEX
IO§
VCC = 0,
VCC = 5.5 V, VO = 5.5 V
VI or VO ≤ 4.5 V
Outputs high
VCC = 5.5 V,
VO = 2.5 V
Outputs high
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
∆ICC¶
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Control inputs
V
2
100
Control inputs
UNIT
V
2
IOH = –32 mA
IOL = 48 mA
IOZPU‡
IOZPD‡
Ci
MIN
2.5
Vhys
II
SN74ABTH32318
TYP†
MAX
MIN
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4
4.5
5V
VOL
SN54ABTH32318
TYP†
MAX
TEST CONDITIONS
100
±1
±1
±20
100
–100
–100
–100
Outputs low
Outputs disabled
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
µA
µA
±50
–50
mV
±20
100
V
±50
µA
±50
±50
µA
±100
±100
µA
50
50
µA
–180
mA
–180
–50
–100
2
2
45
45
1
1
05
0.5
05
0.5
3
mA
mA
3
pF
Cio
A, B, or C ports
11.5
11.5
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This parameter is specified by characterization.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABTH32318
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
th
Hold time
SN74ABTH32318
MIN
150
3.3
3.3
CLK high or low
3.3
3.3
A, B, or C before CLK↑
2.4
2.4
A, B, or C before LE↓
2.1
2.1
A, B, or C after CLK↑
1.4
1.4
A, B, or C after LE↓
2.1
2.1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
150
LE high
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
MAX
UNIT
MHz
ns
ns
ns
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
SN54ABTH32318
MIN
MAX
150
A B
A,
B, or C
C B,
C,
B or A
SEL
A B,
A,
B or C
LE
A B,
A,
B or C
CLK
A B,
B or C
A,
OE
A B,
A,
B or C
OE
A B,
A,
B or C
SN74ABTH32318
MIN
MAX
150
UNIT
MHz
1.4
6.5
1.4
6.1
1.1
6.8
1.1
6.6
1.4
6.7
1.4
6.5
1.8
6.8
1.8
6.5
2.6
8
2.6
7.5
2.6
7.4
2.6
6.9
2.5
8
2.5
7.4
2.5
7.2
2.5
6.7
1.4
6.9
1.4
6.8
2.4
7.2
2.4
7.1
1
6.4
1
6.2
2
6.4
2
6
ns
ns
ns
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54ABTH32318, SN74ABTH32318
18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
SCBS180E – JUNE 1992 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
tPHL
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
VOH
Output
3V
Output
Control
tPHL
VOH
Output
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74ABTH32318PN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
ABTH32318
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
