SN74AC563DWRG4


    
 
 
 
SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003 D D SN54AC563 . . . J OR W PACKAGE SN74AC563 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V 3-State Inverting Outputs Drive Bus Lines Directly Full Parallel Access for Loading Flow-Through Architecture to Optimize PCB Layout OE 1D 2D 3D 4D 5D 6D 7D 8D GND description/ordering information The ’AC563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 2D 1D OE VCC SN54AC563 . . . FK PACKAGE (TOP VIEW) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND CLK 8Q 7Q 3D 4D 5D 6D 7D 1Q D D D D OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION PDIP − N SN74AC563N Tube SN74AC563DW Tape and reel SN74AC563DWR SOP − NS Tape and reel SN74AC563NSR AC563 SSOP − DB Tape and reel SN74AC563DBR AC563 Tube SN74AC563PW Tape and reel SN74AC563PWR CDIP − J Tube SNJ54AC563J SNJ54AC563J CFP − W Tube SNJ54AC563W SNJ54AC563W LCCC − FK Tube SNJ54AC563FK SNJ54AC563FK TSSOP − PW −55°C 125°C −55 C to 125 C TOP-SIDE MARKING Tube SOIC − DW −40°C 85°C −40 C to 85 C ORDERABLE PART NUMBER PACKAGE† TA SN74AC563N AC563 AC563 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated  


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SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H L L H L H L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

    
 
 
 
SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54AC563 VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL VI VO IOH IOL ∆t/∆v MIN MAX 2 6 Input voltage Low-level output current 2 6 3.15 3.15 3.85 3.85 0 High-level output current MAX 2.1 0 Output voltage MIN 2.1 VCC = 4.5 V VCC = 5.5 V Low-level input voltage SN74AC563 0.9 1.35 1.35 1.65 1.65 0 0 VCC VCC VCC = 3 V VCC = 4.5 V −12 −12 −24 −24 VCC = 5.5 V VCC = 3 V −24 −24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 8 8 Input transition rise or fall rate V V 0.9 VCC VCC UNIT V V V mA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ICC Ci SN54AC563 MIN MAX SN74AC563 MIN 2.9 2.9 4.5 V 4.49 4.4 4.4 5.5 V 5.49 5.4 5.4 3V 2.56 2.48 2.46 4.5 V 3.86 3.8 3.76 IOH = −24 mA 5.5 V 4.86 4.8 4.76 IOH = −75 mA† 5.5 V IOH = −12 mA IOL = 12 mA IOL = 24 mA II IOZ TA = 25°C TYP MAX 2.99 IOL = 50 µA VOL MIN 3V IOH = −50 µA VOH VCC IOL = 75 mA† VI = VCC or GND VO = VCC or GND VI = VCC or GND, 3.85 3.85 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 5.5 V 0.001 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 5.5 V 0.36 V 0.5 0.44 1.65 1.65 ±1 µA ±5 µA 80 µA 5.5 V ±0.1 ±1 5.5 V ±0.5 ±5 5.5 V 8 VI = VCC or GND 5V 4.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. UNIT V 3V 5.5 V IO = 0 MAX pF  / #%&!$# #"&# '& # " %&!$0" & ".# '$" % "0")'!"#* $&$"& $$ $# "& '"%$# $&" ".# .$)* "+$ #&!"# &""&0" " &.  $#." & ##" "" '& , #"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

    
 
 
 
SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu Pulse duration, LE high th Hold time, data after LE↓ Setup time, data before LE↓ SN54AC563 MIN SN74AC563 MAX MIN MAX UNIT 6 8 7 ns 2.5 5 3 ns 2 3 2 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54AC563 MIN SN74AC563 MAX MIN MAX UNIT tw tsu Pulse duration, LE high 4 6 5 ns Setup time, data before LE↓ 2 4.5 2.5 ns th Hold time, data after LE↓ 2 3 2 ns switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q MIN TA = 25°C TYP MAX FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q temperature SN54AC563 range, SN74AC563 MIN MAX MIN MAX 3.5 5.3 13 1.5 16.5 3.5 15 3.5 5.6 12 1.5 15.5 3.5 14 3.5 4.6 13 1.5 16.5 3.5 15 3.5 4.8 12 1.5 15.5 3.5 14 2.5 5.3 11 1.5 13.5 2.5 12 3 5.4 11 1.5 14 3.5 12.5 4 6 12.5 1.5 15 4.5 13.5 2 5.1 9.5 1.5 12 2.5 10.5 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER free-air MIN free-air TA = 25°C TYP MAX temperature SN54AC563 UNIT ns ns ns ns range, SN74AC563 MIN MAX MIN MAX 2 5.3 10 1.5 13 2 11.5 2 5.6 9.5 1.5 12.5 2 11 2 4.6 9.5 1.5 12.5 2 11 2 4.8 8.5 1.5 11.5 2 9.5 2 5.3 9 1.5 11.5 2 10 1.5 5.4 8.5 1.5 11 2 9.5 2 6 11 1.5 13.5 2 12 1.5 5.1 8 1.5 10.5 1.5 9 UNIT ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF,  / #%&!$# #"&# '& # " %&!$0" & ".# '$" % "0")'!"#* $&$"& $$ $# "& '"%$# $&" ".# .$)* "+$ #&!"# &""&0" " &.  $#." & ##" "" '& , #"* 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 25 pF 

    
 
 
 
SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input th 50% VCC VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Output Control (low-level enabling) VCC 50% VCC Input 50% VCC tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC tPLZ tPZL VOH 50% VCC VOL 50% VCC 0V Output Waveform 1 S1 at 2 × VCC (see Note B) 50% VCC Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS ≈VCC VOL + 0.3 V VOL tPHZ tPZH tPLH tPHL Out-of-Phase Output 0V VCC 50% VCC 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AC563DBLE OBSOLETE SSOP DB 20 SN74AC563DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AC563NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AC563PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563PWLE OBSOLETE TSSOP PW 20 SN74AC563PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC563PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD TBD Lead/Ball Finish Call TI Call TI MSL Peak Temp (3) Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AC563DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AC563PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AC563DBR SSOP DB 20 2000 346.0 346.0 33.0 SN74AC563PWR TSSOP PW 20 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AC563DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC563 SN74AC563DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC563 SN74AC563N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -40 to 85 SN74AC563N SN74AC563PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC563 SN74AC563PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC563 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of