SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
SN54AC574 . . . J OR W PACKAGE
SN74AC574 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
2-V to 6-V VCC Operation
Inputs Accept Voltages to 6 V
Max tpd of 8.5 ns at 5 V
3-State Outputs Drive Bus Lines Directly
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ′AC574 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
2D
1D
OE
VCC
SN54AC574 . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal
logic state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in a bus-organized system without need
for interface or pullup components.
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
CLK
8Q
7Q
3D
4D
5D
6D
7D
1Q
D
D
D
D
OE does not affect internal operations of the
flip-flop. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
ORDERING INFORMATION
PDIP − N
SN74AC574N
Tube
SN74AC574DW
Tape and reel
SN74AC574DWR
SOP − NS
Tape and reel
SN74AC574NSR
AC574
SSOP − DB
Tape and reel
SN74AC574DBR
AC574
Tube
SN74AC574PW
Tape and reel
SN74AC574PWR
CDIP − J
Tube
SNJ54AC574J
SNJ54AC574J
CFP − W
Tube
SNJ54AC574W
SNJ54AC574W
LCCC − FK
Tube
SNJ54AC574FK
SNJ54AC574FK
TSSOP − PW
−55°C
55 C to 125
125°C
C
†
TOP-SIDE
MARKING
Tube
SOIC − DW
−40°C
40 C to 85°C
85 C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74AC574N
AC574
AC574
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
VCC
Supply voltage
VCC = 3 V
VIH
High-level
High
level input voltage
VIL
Low-level
Low
level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level
High
level output current
IOL
Low-level
Low
level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
SN54AC574
SN74AC574
MIN
MAX
MIN
MAX
2
6
2
6
2.1
2.1
VCC = 4.5 V
3.15
3.15
VCC = 5.5 V
3.85
3.85
UNIT
V
V
VCC = 3 V
0.9
0.9
VCC = 4.5V
1.35
1.35
VCC = 5.5 V
1.65
1.65
V
0
VCC
0
VCC
V
0
VCC
0
VCC
V
VCC = 3 V
−12
−12
VCC = 4.5 V
−24
−24
VCC = 5.5 V
−24
−24
VCC = 3 V
12
12
VCC = 4.5 V
24
24
VCC = 5.5 V
24
24
8
8
ns/V
85
°C
−55
125
−40
mA
mA
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = −50
50 μA
VOH
IOH = −12 mA
IOH = −24
24 mA
IOL = 50 μA
VOL
IOL = 12 mA
IOL = 24 mA
TA = 25°C
MIN
TYP
MAX
SN54AC574
SN74AC574
MIN
MIN
MAX
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.56
2.4
2.46
4.5 V
3.94
3.7
3.76
5.5 V
4.94
4.7
4.76
MAX
UNIT
V
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
V
II
VI = VCC or GND
5.5 V
±0.1
±1
±1
μA
IOZ
VO = VCC or GND
5.5 V
±0.5
±5
±2.5
μA
ICC
VI = VCC or GND,
4
80
40
μA
Ci
VI = VCC or GND
IO = 0
5.5 V
5V
POST OFFICE BOX 655303
4.5
• DALLAS, TEXAS 75265
pF
3
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
th
SN54AC574
MAX
MIN
SN74AC574
MAX
75
MIN
UNIT
MAX
55
60
MHz
6
7.5
7
ns
Setup time, data before CLK↑
2.5
6.5
3
ns
Hold time, data after CLK↑
1.5
2.5
1.5
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
SN54AC574
MAX
MIN
SN74AC574
MAX
95
MIN
UNIT
MAX
fclock
Clock frequency
85
85
MHz
tw
Pulse duration, CLK high or low
4
5
5
ns
tsu
Setup time, data before CLK↑
1.5
3.5
2
ns
th
Hold time, data after CLK↑
1.5
2.5
1.5
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
TO
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLK
Q
OE
Q
OE
Q
TA = 25°C
SN54AC574
MAX
MIN
MAX
SN74AC574
MIN
TYP
MIN
75
112
3.5
8.5
13.5
1
16.5
3.5
15
3.5
7.5
12
1
15
3.5
13.5
2.5
7
11
1
13
2.5
12
3
6.5
10.5
1
12.5
3
11.5
3.5
7.5
12
1
14
2.5
13
2
5.5
9
1
10.5
1.5
10
55
MAX
60
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
TO
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
fmax
95
153
tPLH
2
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLK
Q
OE
Q
OE
Q
SN54AC574
MAX
SN74AC574
MAX
MIN
6
9.5
1.5
11.5
2
11
2
5.5
8.5
1.5
10.5
2
9.5
2
5
8.5
1.5
9.5
2
9
2
5
8
1.5
9.5
1.5
9
2
6
9.5
1.5
11.5
1.5
10.5
1
4.5
7.5
1.5
9
1
8.5
85
MIN
MAX
85
UNIT
MHz
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
40
pF
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Open
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
500 Ω
LOAD CIRCUIT
VCC
50% VCC
Timing Input
0V
tw
tsu
3V
Input 50% VCC
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VCC
Input
50% VCC
50% VCC
0V
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
tPLZ
≈VCC
50%VCC
tPZH
VOH
50% VCC
VOL
50% VCC
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
50% VCC
VCC
50% VCC
tPZL
tPHL
tPLH
In-Phase
Output
Output
Control
(low-level
enabling)
VOL
tPHZ
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
VOL + 0.3 V
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
1-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9677301Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629677301Q2A
SNJ54AC
574FK
5962-9677301QRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9677301QR
A
SNJ54AC574J
5962-9677301QSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9677301QS
A
SNJ54AC574W
SN74AC574DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC574
Samples
SN74AC574DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC574
Samples
SN74AC574DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC574
Samples
SN74AC574N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74AC574N
Samples
SN74AC574PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC574
Samples
SN74AC574PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC574
Samples
SN74AC574PWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AC574
Samples
SNJ54AC574FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629677301Q2A
SNJ54AC
574FK
SNJ54AC574J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9677301QR
A
SNJ54AC574J
SNJ54AC574W
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9677301QS
A
SNJ54AC574W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Aug-2022
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of