SCAS721 − OCTOBER 2003
D Controlled Baseline
D
D
D
D
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
D 2-V to 6-V VCC Operation
D Inputs Accept Voltages to 6 V
D Max tpd of 10 ns at 5 V
D PACKAGE
(TOP VIEW)
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
description/ordering information
The SN74AC74 is a dual positive-edge-triggered D-type flip-flop.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at D can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
−55°C to 125°C
SOIC − D
Tape and reel
SN74AC74MDREP
SAC74MEP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H§
H§
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
§ This configuration is nonstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
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1
SCAS721 − OCTOBER 2003
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCAS721 − OCTOBER 2003
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VI
VO
IOH
IOL
∆t/∆v
MAX
2
6
3.15
0.9
V
1.65
0
Output voltage
0
Low-level output current
V
1.35
Input voltage
High-level output current
V
3.85
VCC = 4.5 V
VCC = 5.5 V
Low-level input voltage
UNIT
2.1
VCC = 5.5 V
VCC = 3 V
VIL
MIN
VCC
VCC
VCC = 3 V
VCC = 4.5 V
−12
VCC = 5.5 V
VCC = 3 V
−24
VCC = 4.5 V
VCC = 5.5 V
24
−24
V
V
mA
12
mA
24
Input transition rise or fall rate
8
ns/V
TA
Operating free-air temperature
−55
125
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 µA
VOH
IOH = −12 mA
IOH = −24 mA
IOL = 50 µA
VOL
IOL = 12 mA
IOL = 24 mA
VCC
TA = 25°C
MIN
TYP
MAX
3V
2.9
4.49
2.9
4.5 V
4.4
5.49
4.4
5.5 V
5.4
5.49
5.4
3V
2.56
2.4
4.5 V
3.86
3.7
5.5 V
4.86
ICC
Ci
Control pins
VI = VCC or GND
VI = VCC or GND,
VI = VCC or GND
4.7
0.1
0.1
4.5 V
0.001
0.1
0.1
5.5 V
0.001
0.1
0.1
3V
0.36
0.5
4.5 V
0.36
0.5
5.5 V
0.36
0.5
±0.1
±1
±0.1
±1
2
40
5.5 V
5V
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UNIT
V
0.002
5.5 V
IO = 0
MAX
3V
Data pins
II
MIN
3
V
µA
A
µA
pF
3
SCAS721 − OCTOBER 2003
timing requirements over recommended operating free-air temperature range,
VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
MIN
100
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
PRE or CLR low
5.5
8
CLK
5.5
8
Data
4
5
PRE or CLR inactive
0
0.5
0.5
0.5
MAX
UNIT
70
MHz
ns
ns
ns
timing requirements over recommended operating free-air temperature range,
VCC = 5 V"0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
MIN
140
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
PRE or CLR low
4.5
5.5
CLK
4.5
5.5
Data
3
4
PRE or CLR inactive
0
0.5
0.5
0.5
MAX
UNIT
95
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
PRE or CLR
Q or Q
CLK
Q or Q
MIN
TA = 25°C
TYP
MAX
MIN
MAX
100
125
3.5
8
12
70
1
13
4
10.5
12
1
14
4.5
8
13.5
1
17.5
3.5
8
14
1
13.5
UNIT
MHz
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V " 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
PRE or CLR
Q or Q
CLK
Q or Q
MIN
TA = 25°C
TYP
MAX
MIN
MAX
140
160
2.5
6
9
95
1
9.5
3
8
9.5
1
10.5
3.5
6
10
1
12
2.5
6
10
1
10
UNIT
MHz
ns
ns
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
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f = 1 MHz
TYP
45
UNIT
pF
SCAS721 − OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Open
TEST
S1
tPLH/tPHL
Open
500 Ω
tw
LOAD CIRCUIT
VCC
VCC
50% VCC
Input
50% VCC
Input
0V
50% VCC
0V
50% VCC
VOH
50% VCC
VOL
VCC
50% VCC
Timing Input
0V
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
tPHL
tPLH
In-Phase
Output
50% VCC
50% VCC
VOH
50% VCC
VOL
th
tsu
Data Input
VCC
50% VCC
50% VCC
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AC74MDREP
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
SAC74MEP
V62/04617-01XE
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
SAC74MEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of