SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003
D
D
D
D
D
D
D
D
SN54ACT1284 . . . J OR W PACKAGE
SN74ACT1284 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
4.5-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 20 ns at 5 V
3-State Outputs Directly Drive Bus Lines
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Designed for the IEEE 1284-I (Level-1 Type)
and IEEE 1284-II (Level-2 Type) Electrical
Specifications
A1
A2
A3
A4
GND
GND
A5
A6
A7
DIR
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
B1
B2
B3
B4
VCC
VCC
B5
B6
B7
HD
SN54ACT1284 . . . FK PACKAGE
(TOP VIEW)
A3
A2
A1
B1
B2
description/ordering information
The ’ACT1284 devices are designed for
asynchronous two-way communication between
data buses. The control function minimizes
external timing requirements.
A4
GND
GND
A5
A6
The devices allow data transmission in either the
A-to-B or the B-to-A direction for bits 1, 2, 3, and
4, depending on the logic level at the
direction-control (DIR) input. Bits 5, 6, and 7,
however, always transmit in the A-to-B direction.
4
3 2 1 20 19
18
5
17
6
16
7
15
14
8
B3
B4
VCC
VCC
B5
A7
DIR
HD
B7
B6
9 10 11 12 13
The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive
is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the
drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel
peripheral-interface specification.
ORDERING INFORMATION
SN74ACT1284DW
Tape and reel
SN74ACT1284DWR
SOP − NS
Tape and reel
SN74ACT1284NSR
ACT1284
SSOP − DB
Tape and reel
SN74ACT1284DBR
AU284
Tube
SN74ACT1284PW
Tape and reel
SN74ACT1284PWR
CDIP − J
Tube
SNJ54ACT1284J
SNJ54ACT1284J
CFP − W
Tube
SNJ54ACT1284W
SNJ54ACT1284W
LCCC − FK
Tube
SNJ54ACT1284FK
SNJ54ACT1284FK
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tube
SOIC − DW
0°C to 70°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
ACT1284
AU284
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
1
SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003
FUNCTION TABLE
INPUTS
DIR
HD
L
L
L
OUTPUT
MODE
Open drain
A to B: Bits 5, 6, 7
Totem pole
B to A: Bits 1, 2, 3, 4
H
Totem pole
B to A: Bits 1, 2, 3, 4 and A to B: Bits 5, 6, 7
H
L
Open drain
A to B: Bits 1, 2, 3, 4, 5, 6, 7
H
H
Totem pole
A to B: Bits 1, 2, 3, 4, 5, 6, 7
logic diagram (positive logic)
HD
DIR
A1, A2, A3, A4
B1, B2, B3, B4
B5, B6, B7
A5, A6, A7
2
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• DALLAS, TEXAS 75265
SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
B-port input and output voltage range, VI and VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . −2 V to 7 V
A-port input and output voltage range, VI and VO (see Note 1) . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulse duration is limited to 20 ns if the input voltage goes more negative than −0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54ACT1284
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
VO
Open-drain output voltage
High-level input voltage
IOL
Low-level output current
MIN
MAX
4.7
5.5
4.7
5.5
2
0.8
0
HD low
B port, HD high
High-level output current
MAX
2
Input voltage
IOH
SN74ACT1284
MIN
0
VCC
5.5
0
0
UNIT
V
V
0.8
V
VCC
5.5
V
−14
−14
A port
−4
−4
B port
14
14
A port
4
4
V
mA
mA
TA
Operating free-air temperature
−55
125
0
70
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETER
Vhys
VOH
II
IOZ
SN54ACT1284
VCC†
MIN
TYP
SN74ACT1284
MAX
MIN
Input
hysteresis
5V
0.4
0.4
VIT+ − VIT− for all inputs
4.7 V
0.2
0.2
B port
IOH = −14 mA
4.7 V
2.4
2.4
IOH = −50 µA
MIN
to MAX
VCC−0.2
VCC −0.2
IOH = −4 mA
IOL = 14 mA
4.7 V
A port
B port
VOL
TEST CONDITIONS
A or B ports‡
Ioff
ICC
B port
Ci
Control inputs
Cio
A or B ports
MAX
UNIT
V
V
3.7
4.7 V
IOL = 50 µA
IOL = 4 mA
A port
3.7
TYP
4.7 V
0.4
0.4
0.2
0.2
0.4
0.4
±1
±1
µA
µA
V
VI = VCC or GND
VO = VCC or GND
5.5 V
5.5 V
±20
±20
VI or VO ≤ 7 V
VI = VCC or GND,
0V
±100
±100
µA
1.5
1.5
mA
IO = 0
VI = VCC or GND
VO = VCC or GND
5.5 V
5V
4
4
pF
5V
12
12
pF
ZO
B port
IOH = −20 mA,
IOH = −50 mA
5V
8
30
† For I/O ports, the parameter IOZ includes the input leakage current II.
‡ For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
8
30
Ω
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
Totem pole
SR
Totem pole
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
B output
tpd(EN)
tpd(DIS)
Totem pole
HD
B
tr, tf
Open drain
A
B
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4
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• DALLAS, TEXAS 75265
SN54ACT1284
SN74ACT1284
MIN
MAX
MIN
MAX
1
20
1
20
1
20
1
20
0.05
0.4
0.05
0.4
1
20
1
20
1
20
1
20
120
120
UNIT
ns
V/ns
ns
ns
SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
From B Output
Under Test
62 Ω
CL = 50 pF
(see Note A)
TP1
tPHL
33 Ω
3V
Input
(see Note C)
0V
Output
(see Note D)
Sink Load
1.5 V
1.5 V
tPLH
tPHL
VOH
VOH − 1.4 V
VOL
VOH
VOL + 1.4 V
tPLH
VOL
Source Load
62 Ω
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
CL = 50 pF
(see Note A)
A-TO-B LOAD (totem pole)
3V
Input
(see Note F)
VCC
1.5 V
1.5 V
0V
TP1
2V
0.8 V
VOL
(see Note E)
500 Ω
2V
0.8 V
VOH
VOL
tf
tr
From B Output
VOLTAGE WAVEFORMS MEASURED AT TP1 (B SIDE)
CL = 50 pF
(see Note A)
A-TO-B LOAD (open drain)
Input
(see Note F)
1.5 V
0V
From A Output
Under Test
CL = 50 pF
(see Note A)
3V
1.5 V
tPLH
500 Ω
tPHL
VOH
Output
50% VCC
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
B-TO-A LOAD (totem pole)
NOTES: A.
B.
C.
D.
E.
F.
CL includes probe and jig capacitance.
The outputs are measured one at a time with one transition per measurement.
Input rise and fall times are 3 ns, 150 ns < pulse duration