SN74ACT16374QDLREP

SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – REVISED JULY 2002 D D D D D D D D D D DL PACKAGE (TOP VIEW) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pins Minimize High-Speed Switching Noise 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. description The SN74ACT16374Q-EP is a 16-bit edge-triggered D-type flip-flop with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. An output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system, without need for interface or pullup components. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 125°C SSOP – DL Tape and reel SN74ACT16374QDLREP ACT16374QEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – REVISED JULY 2002 FUNCTION TABLE (each section) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic diagram (positive logic) 1OE 1CLK 1 2OE 48 2CLK C1 1D1 47 2 1D 24 25 C1 1Q1 2D1 36 1D 13 2Q1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±24 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±24 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±260 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – REVISED JULY 2002 recommended operating conditions (see Note 3) MIN NOM MAX 4.5 5 5.5 VCC VIH Supply voltage (see Note 4) VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL Dt/Dv Low-level output current High-level input voltage 2 V V High-level output current Input transition rise or fall rate UNIT 0 0.8 V VCC VCC V –16 mA V 16 mA 10 ns/V TA Operating free-air temperature –40 125 °C NOTES: 3. All unused inputs of the device must be at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4. All VCC and GND pins must be connected to the proper-voltage power supply. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 50 mA IOH = –50 VOH IOH = –16 16 mA IOH = –24 mA{ IOL = 16 mA MIN 4.5 V 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.7 5.5 V 4.94 4.7 MAX VI = VCC or GND VO = VCC or GND ICC VI = VCC or GND, IO = 0 DICC‡ One input at 3.4 V, Other inputs at GND or VCC Ci VI = VCC or GND VO = VCC or GND V 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.5 5.5 V 0.36 0.5 5.5 V II IOZ UNIT 3.85 4.5 V IOL = 24 mA{ Co TA = 25°C TYP MAX 5.5 V IOL = 50 mA VOL MIN V 0.5 5.5 V ±0.1 ±1 5.5 V ±0.5 ±10 5.5 V 8 160 mA mA mA 5.5 V 0.9 1 mA 5V 4.5 pF 5V 12 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL-voltage levels rather than 0 V to VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – REVISED JULY 2002 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 tw Pulse duration tsu th Setup time, data before CLK↑ MIN MAX UNIT 0 65 MHz 65 CLK low 7.5 7.5 CLK high 4.5 4.5 6.5 6.5 ns 1 1 ns Hold time, data after CLK↑ ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX MIN 65 CLK Q OE Q OE Q MAX 65 UNIT MHz 5.1 8.8 10.9 5.1 13.2 5.3 8.8 10.9 5.3 13.1 3.7 8.4 10.5 3.7 12.7 4.4 9.7 11.9 4.4 14.3 5.4 7.9 9.8 5.4 10.9 4.9 7.2 9.1 4.9 10.2 ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d 4 Power dissipation capacitance per flip-flop flip flop POST OFFICE BOX 655303 TEST CONDITIONS Outputs enabled Outputs disabled • DALLAS, TEXAS 75265 CL = 50 pF, pF f = 1 MHz TYP 52 38 UNIT pF SN74ACT16374Q-EP 16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS SCAS679B – MAY 2002 – REVISED JULY 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH /tPHL tPLZ /tPZL tPHZ /tPZH Open 2 × VCC GND LOAD CIRCUIT 3V Timing Input (see Note B) 1.5 V 0V tw tsu 3V Input 1.5 V th 1.5 V 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPZL 50% VCC VOH 50% VCC VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output VOH 50% VCC VOL 3V 1.5 V 50% VCC tPZH 20% VCC VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS ≈VCC 50% VCC 80% VCC VOH ≈0 V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74ACT16374QDLREP ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 ACT16374QEP V62/03603-01XE ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 ACT16374QEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of