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SN54ACT244, SN74ACT244
SCAS517D – JUNE 1995 – REVISED AUGUST 2016
SNx4ACT244 Octal Buffers and Drivers With 3-State Outputs
1 Features
3 Description
•
•
•
•
•
These SNx4ACT244 octal buffers and drivers are
designed specifically to improve the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and transmitters.
1
4.5-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 9.5 ns at 5 V
Inputs are TTL Compatible
On Products Compliant to MIL-PRF-38535,
All Parameters are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
The SNx4ACT244 devices are organized as two 4-bit
buffers and drivers with separate output-enable (OE)
inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs.
When OE is high, the outputs are in the highimpedance state.
Device Information(1)
2 Applications
•
•
•
PART NUMBER
LED displays
Servers and Telecommunication
Switching Networks
PACKAGE
BODY SIZE (NOM)
SN74ACT244DB
SSOP (20)
7.20 mm × 5.30 mm
SN74ACT244DW
SOIC (20)
12.80 mm × 7.50
mm
SN74ACT244N
PDIP (20)
24.33 mm × 6.35
mm
SN74ACT244NS
SO (20)
12.60 mm × 7.80
mm
SN74ACT244PW
TSSOP (20)
6.50 mm × 6.40 mm
SNJ54ACT244FK
LCCC (20)
8.89 mm × 8.89 mm
SNJ54ACT244J
CDIP (20)
24.20 mm × 6.92
mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1OE
1A1
1A2
1
19
2OE
2
18
4
16
6
14
1A3
1A4
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54ACT244, SN74ACT244
SCAS517D – JUNE 1995 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2002) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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SCAS517D – JUNE 1995 – REVISED AUGUST 2016
5 Pin Configuration and Functions
SN54ACT244: J or W Packages
20-Pin CDIP or CFP
Top View
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
20
2
19
3
18
4
17
5
6
7
8
9
10
16
15
14
13
12
11
SN74ACT244: DB, DW, N, NS, or PW Packages
20-Pin SSOP, SOIC, PDIP, SO, or TSSOP
Top View
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1Y1
2A4
1Y2
2A3
1Y3
2Y1
GND
2A1
1Y4
2A2
1A2
2Y3
1A3
2Y2
1A4
2OE
2Y4
1A1
1OE
VCC
SN54ACT244: FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
1OE
I
1 Active low Output enable
2
1A1
I
1A1 input
3
2Y4
O
2Y4 output
4
1A2
I
1A2 input
5
2Y3
O
2Y3 Output
6
1A3
I
1A3 input
7
2Y2
O
2Y2 Output
8
1A4
I
1A4 input
9
2Y1
O
2Y1 Output
10
GND
—
Ground
11
2A1
I
2A1 input
12
1Y4
O
1Y4 output
13
2A2
I
2A2 input
14
1Y3
O
1Y3 Output
15
2A3
I
2A3 input
16
1Y2
O
1Y2 Output
17
2A4
I
2A4 input
18
1Y1
O
1Y1 Output
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SCAS517D – JUNE 1995 – REVISED AUGUST 2016
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Pin Functions (continued)
PIN
NO.
I/O
NAME
19
2OE
I
20
VCC
—
DESCRIPTION
2 Active low Output enable
Power
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
7
V
VI
Input voltage (2)
–0.5
VCC + 0.5
V
–0.5
(2)
VO
Output voltage
VCC + 0.5
V
IIK
Input clamp current
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±50
mA
Continuous current through VCC or GND
±200
mA
TJ
Absolute Maximum Junction Temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
UNIT
SN74ACT244 in DW Package
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±2000
V
SN54ACT244 in J, W, DB, N, NS, PW, FK Packages
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
24
mA
Δt/Δv
Input transition rise or fall rate
8
ns/V
TA
Operating free-air temperature
(1)
4
2
V
V
0.8
V
0
VCC
V
0
VCC
V
–24
mA
SN54ACT244
–55
125
SN74ACT244
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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SCAS517D – JUNE 1995 – REVISED AUGUST 2016
6.4 Thermal Information
SN74ACT244
THERMAL METRIC
(1)
DB
(SSOP)
DW
(SOIC)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
94.1
81.4
48.1
76.4
103
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
55.6
46.8
34.1
42.6
37.7
°C/W
RθJB
Junction-to-board thermal resistance
49.3
49.3
29
43.9
54
°C/W
ψJT
Junction-to-top characterization
parameter
20.8
20
19.5
18.8
2.8
°C/W
ψJB
Junction-to-board characterization
parameter
48.9
48.8
28.9
43.5
53.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
SN54ACT244
4.5 V
SN74ACT244
IOH = –50 µA
4.5 V
4.7
4.76
IOH = –50 mA (1)
SN54ACT244
5.5 V
3.85
IOH = –75 mA (1)
SN74ACT244
5.5 V
3.85
TA = 25°C
0.001
4.5 V
0.1
TA = 25°C
SN54ACT244
0.001
5.5 V
0.1
TA = 25°C
SN54ACT244
0.36
4.5 V
0.5
SN74ACT244
IOL = 24 mA
0.36
5.5 V
0.5
SN74ACT244
0.44
IOL = 50 mA (1)
SN54ACT244
5.5 V
IOL = 75 mA (1)
SN74ACT244
5.5 V
1.65
1.65
TA = 25°C
VO = VCC or GND
SN54ACT244
±0.25
5.5 V
±5
SN74ACT244
(1)
V
0.44
TA = 25°C
SN54ACT244
0.1
0.1
SN74ACT244
VOL
0.1
0.1
SN74ACT244
IOL = 50 µA
IOZ
V
3.7
4.86
5.5 V
SN74ACT244
SN54ACT244
5.49
5.4
3.76
TA = 25°C
SN54ACT244
UNIT
4.4
3.86
SN74ACT244
IOH = –24 mA
MAX
5.4
TA = 25°C
SN54ACT244
4.49
5.4
5.5 V
SN74ACT244
VOH
TYP
4.4
4.4
TA = 25°C
SN54ACT244
MIN
µA
±2.5
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
TA = 25°C
II
VI = VCC or GND
MAX
±0.1
SN54ACT244
5.5 V
±1
SN74ACT244
VI = VCC or GND, IO = 0
4
SN54ACT244
5.5 V
80
SN74ACT244
ΔICC
µA
40
TA = 25°C
One input at 3.4 V,
Other inputs at GND or VCC
(2)
µA
±1
TA = 25°C
ICC
UNIT
0.6
SN54ACT244
5.5 V
1.6
SN74ACT244
mA
1.5
CI
VI = VCC or GND
TA = 25°C
5V
2.5
pF
Co
VI = VCC or GND
TA = 25°C
5V
8
pF
(2)
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
6.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
A
Y
tPHL
tPZH
OE
Y
tPZL
tPHZ
OE
Y
tPLZ
TEST CONDITIONS
MIN
TYP
TA = 25°C
2
6.5
SN54ACT244
1
SN74ACT244
1.5
TA = 25°C
2
MAX
UNIT
9
10
10
7
SN54ACT244
1
10
SN74ACT244
1.5
10
TA = 25°C
1.5
7
8.5
SN54ACT244
1
9.5
SN74ACT244
1
9.5
TA = 25°C
2
7
1
11
SN74ACT244
1.5
10.5
TA = 25°C
2
SN54ACT244
1
11
SN74ACT244
1.5
10.5
TA = 25°C
2.5
7.5
ns
9.5
SN54ACT244
8
ns
9
9.5
ns
10
SN54ACT244
1
11.5
SN74ACT244
2
10.5
6.7 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance per buffer/driver
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TEST CONDITIONS
CL = 50 pF,
f = 1 MHz
TYP
45
UNIT
pF
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SCAS517D – JUNE 1995 – REVISED AUGUST 2016
VOH min (V)
6.8 Typical Characteristics
5.4
5.3
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
-75
VCC 5.5V
-65
-55
-45
-35
IOH mA
-25
-15
-5
D001
Figure 1. VOH Vs IOH
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7 Parameter Measurement Information
2 × VCC
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Open
500 Ω
LOAD CIRCUIT
Output
Control
(low-level
enabling)
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
50% VCC
S1
Open
2 × VCC
Open
3V
1.5 V
50% VCC
VOL
1.5 V
0V
tPLZ
tPZL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
VOH
Output
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Output
Waveform 2
S1 at Open
(see Note B)
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SNx4ACT244 devices are buffer drivers with separate output enable inputs. The active low output enable
ensure the outputs are in high impedance when high. To ensure the high-impedance state during power up or
power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver.
8.2 Functional Block Diagram
1OE
1A1
1A2
1
19
2OE
2
18
4
16
6
14
1A3
1A4
12
8
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
The SNx4ACT244 devices are recommended for 4.5 V to 5.5-V VCC range under normal operating conditions.
The inputs are TTL compatible accepting 2-V minimum high at 5-V VCC.
8.4 Device Functional Modes
Table 1 lists the functions of the device.
Table 1. Function Table (Each Buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Hi-Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SNx4ACT244 is high-drive buffer drivers providing 24-mA current drive per channel at nominal operating
specifications. It can be used as LED driver with appropriate current-limiting resistors to ground or VCC withing
the device's and LED's operating characteristics.
9.2 Typical Application
Vcc
Control signal
1k
LED
SNx4ACT244
Vcc
Vcc
Control signal
1k
LED
SNx4ACT244
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Typical LED driving application
9.2.1 Design Requirements
The pullup and pulldown current limiting resistors are chosen to operate within the LED and the SNx4ACT244
device operating specifications. A 1-kΩ resistor, limits the current to less than 5 mA at 5-V VCC operation.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For the specified high and low levels See (VIH and VIL) in the Recommended Operating Conditions.
– Inputs are not overvoltage tolerant and must be limited to VCC.
2. Recommended output conditions:
– Limit the output voltage to VCC.
– Choose the current-limiting resistor for the LED to limit the output current to IO as per the
Recommended Operating Conditions.
10
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Typical Application (continued)
VOL max (V)
9.2.3 Application Curve
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
VCC 5.5V
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
IOL (mA)
D001
Figure 5. VOL vs IOL
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10 Power Supply Recommendations
The power supply may be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01-µF or 0.022-µF
capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to
reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies
of noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
Inputs should not float when using multiple bit logic devices. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND
gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected
because the undefined voltages at the outside connections result in undefined operational states.
Specified in the Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally, they will be tied to
GND or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Output
Unused Input
Input
Figure 6. Layout Example
12
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004).
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54ACT244
Click here
Click here
Click here
Click here
Click here
SN74ACT244
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54ACT244 SN74ACT244
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8776001M2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59628776001M2A
SNJ54ACT
244FK
5962-8776001MRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8776001MR
A
SNJ54ACT244J
5962-8776001MSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8776001MS
A
SNJ54ACT244W
5962-8776001SRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8776001SR
A
SNV54ACT244J
5962-8776001SSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8776001SS
A
SNV54ACT244W
SN74ACT244DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD244
Samples
SN74ACT244DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT244
Samples
SN74ACT244DWE4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT244
Samples
SN74ACT244DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT244
Samples
SN74ACT244DWRE4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT244
Samples
SN74ACT244DWRG4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT244
Samples
SN74ACT244N
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74ACT244N
Samples
SN74ACT244NE4
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74ACT244N
Samples
SN74ACT244NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT244
Samples
SN74ACT244NSRG4
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT244
Samples
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74ACT244PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD244
Samples
SN74ACT244PWE4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD244
Samples
SN74ACT244PWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD244
Samples
SN74ACT244PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
AD244
Samples
SN74ACT244PWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD244
Samples
SN74ACT244PWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD244
Samples
SNJ54ACT244FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59628776001M2A
SNJ54ACT
244FK
SNJ54ACT244J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8776001MR
A
SNJ54ACT244J
SNJ54ACT244W
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8776001MS
A
SNJ54ACT244W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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