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SN74ACT32N

SN74ACT32N

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    PDIP14

  • 描述:

    IC GATE OR 4CH 2-INP 14DIP

  • 数据手册
  • 价格&库存
SN74ACT32N 数据手册
         SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003 D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 10 ns at 5 V D Inputs Are TTL-Voltage Compatible SN54ACT32 . . . J OR W PACKAGE SN74ACT32 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 1Y NC 2A NC 2B 4B 1B 1A NC VCC VCC 4B 4A 4Y 3B 3A 3Y 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1A 1B 1Y 2A 2B 2Y GND SN54ACT32 . . . FK PACKAGE (TOP VIEW) NC − No internal connection description/ordering information The ’ACT32 devices are quadruple 2-input positive-OR gates. The devices perform the Boolean function Y = A + B or Y = A • B in positive logic. ORDERING INFORMATION PDIP − N SN74ACT32N Tube SN74ACT32D Tape and reel SN74ACT32DR SOP − NS Tape and reel SN74ACT32NSR ACT32 SSOP − DB Tape and reel SN74ACT32DBR AD32 Tube SN74ACT32PW Tape and reel SN74ACT32PWR CDIP − J Tube SNJ54ACT32J SNJ54ACT32J CFP − W Tube SNJ54ACT32W SNJ54ACT32W LCCC − FK Tube SNJ54ACT32FK SNJ54ACT32FK TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube SOIC − D −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA SN74ACT32N ACT32 AD32 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS B OUTPUT Y H X H X H H L L L A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated     !"#$% !%&%    %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(#  )$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/, ("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++ )&(&#$$(, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1          SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003 logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54ACT32 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL ∆t/∆v Low-level output current High-level input voltage SN74ACT32 MIN 2 2 0.8 Input transition rise or fall rate UNIT V V 0.8 V VCC VCC V −24 −24 mA 24 24 mA 8 8 ns/V VCC VCC 0 0 V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.    %'(#&% !%!$(% )("! % $ '(#&1$ ( $0% )&$ ' $1$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0  !&%0$ ( !%%"$ $$ )("! ." %!$, 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265          SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 µA A VOH IOH = −24 mA IOH = −50 mA† IOH = −75 mA† SN54ACT32 4.5 V 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 MIN MAX MIN MAX UNIT 4.4 V 3.86 5.5 V IOL = 24 mA SN74ACT32 MIN 5.5 V IOL = 50 µA A VOL TA = 25°C TYP MAX VCC 3.85 4.5 V 0.001 0.1 0.1 0.1 5.5 V 0.001 0.1 0.1 0.1 5.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 V IOL = 50 mA† IOL = 75 mA† 5.5 V II ICC VI = VCC or GND VI = VCC or GND, 5.5 V ±0.1 ±1 ±1 µA 5.5 V 2 40 20 µA nICC‡ One input at 3.4 V, Other inputs at VCC or GND 1.6 1.5 mA 1.65 5.5 V IO = 0 1.65 5.5 V 0.6 Ci VI = VCC or GND 5V 2.6 † Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. pF switching characteristics over recommended operating free-air temperature range, VCC = 5 V " 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y MIN TA = 25°C TYP MAX SN54ACT32 MIN MAX SN74ACT32 MIN MAX 1 6.5 9 1 10 1 6.5 9 1 10 UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, f = 1 MHz TYP UNIT 40 pF    %'(#&% !%!$(% )("! % $ '(#&1$ ( $0% )&$ ' $1$+)#$%, &(&!$(! && &% $( )$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0  !&%0$ ( !%%"$ $$ )("! ." %!$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3          SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION TEST S1 tPLH/tPHL Open From Output Under Test CL = 50 pF (see Note A) S1 Open 1.5 V 1.5 V 0V tPHL tPLH 2 × VCC 500 Ω 3V Input (see Note B) In-Phase Output 50% VCC tPLH tPHL 500 Ω Out-of-Phase Output LOAD CIRCUIT VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74ACT32D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 Samples SN74ACT32DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD32 Samples SN74ACT32DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 Samples SN74ACT32DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 Samples SN74ACT32N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74ACT32N Samples SN74ACT32NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT32 Samples SN74ACT32PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD32 Samples SN74ACT32PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD32 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
SN74ACT32N 价格&库存

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