SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
SN54ACT573 . . . J OR W PACKAGE
SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
4.5-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 9.5 ns at 5 V
Inputs Are TTL-Voltage Compatible
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
2D
1D
OE
VCC
SN54ACT573 . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
3D
4D
5D
6D
7D
1Q
D
D
D
D
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
PDIP − N
−55°C
55 C to 125
125°C
C
†
TOP-SIDE
MARKING
Tube
SN74ACT573N
Tube
SN74ACT573DW
Tape and reel
SN74ACT573DWR
SOP − NS
Tape and reel
SN74ACT573NSR
ACT573
SSOP − DB
Tape and reel
SN74ACT573DBR
AD573
TSSOP − PW
Tape and reel
SN74ACT573PWR
AD573
CDIP − J
Tube
SNJ54ACT573J
SNJ54ACT573J
CFP − W
Tube
SNJ54ACT573W
SNJ54ACT573W
LCCC − FK
Tube
SNJ54ACT573FK
SNJ54ACT573FK
SOIC − DW
−40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74ACT573N
ACT573
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
1
OE
LE
11
C1
1D
19
1Q
2
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through, VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
recommended operating conditions (see Note 3)
SN54ACT573
SN74ACT573
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
−24
−24
mA
IOL
Low-level output current
24
24
mA
Δt/Δv
Input transition rise or fall rate
8
ns/V
TA
Operating free-air temperature
85
°C
2
2
0.8
8
−55
125
−40
V
V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50
50 μA
A
VOH
IOH = − 24 mA
4.4
4.49
4.4
4.4
5.5 V
5.4
5.49
5.4
5.4
4.5 V
3.86
3.7
3.76
5.5 V
4.86
4.7
4.76
5.5 V
VI = VCC or GND
VI = VCC or GND,
ΔICC‡
One input at 3.4 V,
Other inputs at GND or VCC
Ci
VI = VCC or GND
IO = 0
MAX
UNIT
V
3.85
3.85
0.1
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
5.5 V
ICC
MIN
0.1
5.5 V
II
MAX
5.5 V
mA†
VO = VCC or GND
MIN
4.5 V
IOL = 50 mA†
IOL = 75
MAX
SN74ACT573
4.5 V
IOH = −75 mA†
IOZ
SN54ACT573
TYP
5.5 V
IOL = 24 mA
TA = 25°C
MIN
IOH = −50 mA†
IOL = 50 μA
A
VOL
VCC
0.1
V
1.65
1.65
5.5 V
±0.25
5.5 V
±0.1
5.5 V
4
15
1.5
55V
5.5
06
0.6
5V
5
±5
±2.5
μA
±1
±1
μA
80
40
μA
15
1.5
mA
pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V .
CC
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
Pulse duration, LE high
tsu
th
MAX
SN54ACT573
MIN
MAX
SN74ACT573
MIN
MAX
UNIT
3.5
5
4
ns
Setup time, data before LE↓
3
4.5
3.5
ns
Hold time, data after LE↓
0
1
0
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
D
Q
LE
Q
OE
Q
OE
Q
TA = 25°C
SN54ACT573
SN74ACT573
MIN
TYP
MAX
MIN
MAX
MIN
MAX
2.5
6
10.5
1.5
13.5
2
12
2.5
6
10.5
1.5
13.5
2
12
3
6
10.5
1.5
13
2.5
12
2.5
5.5
9.5
1.5
12
2
10.5
2
5.5
10
1.5
11.5
1.5
11
1.5
5.5
9.5
1.5
11
1.5
10.5
2.5
6.5
11
1.5
13.5
1.5
12.5
1.5
5
8.5
1.5
10.5
1
9.5
UNIT
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
25
UNIT
pF
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Open
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
3V
1.5 V
Timing Input
LOAD CIRCUIT
0V
th
tsu
3V
1.5 V
Data Input
tw
0V
3V
1.5 V
Input
1.5 V
VOLTAGE WAVEFORMS
1.5 V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
1.5 V
1.5 V
0V
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
≈VCC
50% VCC
tPZH
tPHL
VOH
50% VCC
tPLZ
50% VCC
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-87664012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596287664012A
SNJ54ACT
573FK
5962-8766401RA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8766401RA
SNJ54ACT573J
Samples
5962-8766401SA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8766401SA
SNJ54ACT573W
Samples
SN74ACT573DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD573
Samples
SN74ACT573DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT573
Samples
SN74ACT573DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT573
Samples
SN74ACT573N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74ACT573N
Samples
SN74ACT573NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT573
Samples
SN74ACT573PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD573
Samples
SN74ACT573PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AD573
Samples
SNJ54ACT573FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
596287664012A
SNJ54ACT
573FK
SNJ54ACT573J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8766401RA
SNJ54ACT573J
Samples
SNJ54ACT573W
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8766401SA
SNJ54ACT573W
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of