SN74ACT7805-40DLR

SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized to Independent System Clocks Input-Ready Flag Synchronized to Write Clock Output-Ready Flag Synchronized to Read Clock 256 Words by 18 Bits Low-Power Advanced CMOS Technology Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag Bidirectional Configuration and Width Expansion Without Additional Logic Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously Data Rates up to 67 MHz Pin-to-Pin Compatible With SN74ACT7803 and SN74ACT7813 Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing description DL PACKAGE (TOP VIEW) RESET D17 D16 D15 D14 D13 D12 D11 D10 VCC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 HF PEN AF/AE WRTCLK WRTEN2 WRTEN1 IR 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 OE1 Q17 Q16 Q15 GND Q14 VCC Q13 Q12 Q11 Q10 Q9 GND Q8 Q7 Q6 Q5 VCC Q4 Q3 Q2 GND Q1 Q0 RDCLK RDEN OE2 OR 28 29 The SN74ACT7805 is a 256-word × 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OEC) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and OEC are trademarks of Texas Instruments Incorporated. Copyright  1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 logic symbol† 1 RESET WRTCLK WRTEN1 Φ FIFO 256 × 18 SN74ACT7805 RESET 25 WRTCLK 27 & WRTEN 26 WRTEN2 RDCLK IN RDY 32 RDCLK HALF-FULL 56 OE1 & 30 EN1 ALMOST FULL/EMPTY OE2 OUT RDY 28 22 24 29 IR HF AF/AE OR & RDEN 31 RDEN PEN D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 23 21 PROGRAM ENABLE 0 0 34 19 36 18 37 17 38 16 40 15 41 14 42 12 43 11 45 Data Data 1 9 46 8 47 7 48 6 49 5 51 4 53 3 54 2 55 17 17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 33 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 functional block diagram OE1 OE2 Output Control D0–D17 Location 1 RDCLK RDEN Synchronous Read Control Location 2 Read Pointer 256 × 18 RAM WRTCLK WRTEN1 WRTEN2 Synchronous Write Control Write Pointer Location 255 Location 256 Register RESET StatusFlag Logic Reset Logic Q0–Q17 OR IR HF AF/AE PEN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 Terminal Functions TERMINAL I/O DESCRIPTION 24 O Almost-full/almost-empty flag. Depth offset values can be programmed for AF/AE, or the default value of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or fewer words or (256 – Y) or more words. AF/AE is high after reset. 21–14, 12–11, 9–2 I 18-bit data input port HF 22 O Half-full flag. HF is high when the FIFO memory contains 128 or more words. HF is low after reset. IR 28 O Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full and writes are disabled. IR is low during reset and goes high on the second low-to-high transition of WRTCLK after reset. 56, 30 I Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO on a low-to-high transition of RDCLK. When either OE1 or OE2 is high, reads are disabled and the data outputs are in the high-impedance state. NAME AF/AE D0–D17 OE1, OE2 4 NO. OR 29 O Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low during reset and goes high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory. PEN 23 I Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D6 is latched as an AF/AE offset value when PEN is low and WRTCLK is high. Q0–Q17 33–34, 36–38, 40–43, 45–49, 51, 53–55 O 18-bit data output port. After the first valid write to empty memory, the first word is output on Q0–Q17 on the third rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When OR is low, the last word read from the FIFO is present on Q0–Q17. RDCLK 32 I Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A low-to-high transition of RDCLK reads data from memory when OE1, OE2, and RDEN are low and OR is high. OR is synchronous to the low-to-high transition or RDCLK. RDEN 31 I Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on the low-to-high transition of RDCLK. RESET 1 I Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. WRTCLK 25 I Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTEN1 is high, and IR is high. IR is synchronous to the low-to-high transition of WRTCLK. WRTEN1, WRTEN2 27, 26 I Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO on a low-to-high transition of WRTCLK. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 RESET 1 0 PEN 1 WRTCLK 2 3 4 1 2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ WRTEN1 Don’t Care WRTEN2 Don’t Care Don’t Care D0–D17 1 RDCLK 2 3 4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ OE1 Don’t Care RDEN Don’t Care OE2 Don’t Care Q0–Q17 Invalid OR Don’t Care AF/AE Don’t Care HF Don’t Care IR Don’t Care Define the AF/AE Flag Using the Default Value of X = Y = 32 Figure 1. Reset Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 RESET 1 0 PEN 1 0 WRTCLK 1 0 WRTEN1 WRTEN2 D0–D17 RDCLK ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W1 W2 W3 W4 1 2 3 W(X+2) W129 W257 OE1 1 0 RDEN 1 0 OE2 1 0 Q0–Q17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Invalid W1 OR AF/AE HF IR Figure 2. Write 6 W(257–Y) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 1 0 RESET 1 PEN 0 WRTCLK 1 2 WRTEN1 WRTEN2 D0–D17 1 0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W257 RDCLK 1 0 OE1 RDEN OE2 Q0–Q17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ W1 W2 W3 W(Y+1) W(Y+2) W129 W130 W(256–X) W(257–X) W256 W257 OR AF/AE HF IR Figure 3. Read POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 offset values for AF/AE The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the offsets are not programmed, the default values of X = Y = 32 are used. The AF/AE flag is high when the FIFO contains X or fewer words or (256 – Y) or more words. Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR is high and WRTCLK is low. On the following low-to-high transition of WRTCLK, the binary value on D0–D6 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of WRTCLK reprograms Y to the binary value on D0–D6 at the time of the second WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are disabled regardless of the state of the write enables (WRTEN1, WRTEN2). A maximum value of 127 can be programmed for either X or Y (see Figure 4). To use the default values of X = Y = 32, PEN must be held high. RESET 3 4 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ WRTCLK PEN D0–D6 X and Y Y IR WRTEN1 WRTEN2 Figure 4. Programming X and Y Separately absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 recommended operating conditions ’ACT7805-15 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL Low level output current Low-level TA Operating free-air temperature High-level input voltage High-level output current ’ACT7805-20 ’ACT7805-25 ’ACT7805-40 MIN MAX MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 2 2 2 2 UNIT V V 0.8 0.8 0.8 0.8 V Q outputs, flags –8 –8 –8 –8 mA Q outputs 16 16 16 16 8 8 8 8 Flags 0 70 0 70 0 70 0 70 mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC‡ Ci Flags Q outputs TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, IOH = –8 mA IOL = 8 mA VCC = 4.5 V, VCC = 5.5 V, IOL = 16 mA VI = VCC or 0 MIN TYP† One input at 3.4 V, UNIT V 0.5 0.5 VCC = 5.5 V, VO = VCC or 0 VI = VCC – 0.2 V or 0 VCC = 5.5 V, VI = 0, MAX 2.4 Other inputs at VCC or GND V ±5 µA ±5 µA 400 µA 1 mA f = 1 MHz 4 pF VO = 0, f = 1 MHz † All typical values are at VCC = 5 V, TA = 25°C. ‡ This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. 8 pF Co POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 timing requirements over recommended operating conditions (unless otherwise noted) (see Figures 1 through 5) ’ACT7805-15 MIN fclock tw Clock frequency Pulse duration tsu Setup time Setu th Hold time MAX ’ACT7805-20 MIN 67 MAX ’ACT7805-25 MIN 50 MAX ’ACT7805-40 MIN 40 MAX 25 WRTCLK high or low 6 7 8 12 RDCLK high or low 6 7 8 12 PEN low 8 9 9 12 D0–D17 before WRTCLK↑ 4 5 5 5 WRTEN1, WRTEN2 before WRTCLK↑ 4 5 5 5 OE1, OE2 before RDCLK↑ 5 5 6 6 RDEN before RDCLK↑ 4 5 5 5 Reset: RESET low before first WRTCLK↑ and RDCLK↑† 5 6 6 6 PEN before WRTCLK↑ 5 6 6 6 Define AF/AE: PEN before WRTCLK↑ 5 6 6 6 D0–D17) after WRTCLK↑ 0 0 0 0 WRTEN1, WRTEN2 after WRTCLK↑ 0 0 0 0 OE1, OE2, RDEN after RDCLK↑ 0 0 0 0 Reset: RESET low after fourth WRTCLK↑ and RDCLK↑† 2 2 2 2 Define AF/AE: PEN after WRTCLK↑ 2 2 2 2 UNIT MHz ns ns ns † To permit the clock pulse to be utilized for reset purposes switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 5) PARAMETER FROM (INPUT) fmax WRTCLK or RDCLK tpd tpd‡ tpd d TO (OUTPUT) RDCLK↑ Any Q RDCLK↑ Any Q ’ACT7805-15 TYP† MAX ’ACT7805-20 MIN MIN 67 50 4 9.5 12 4 MAX ’ACT7805-25 MIN MAX 40 13 4 ’ACT7805-40 MIN MAX 25 15 4 MHz 20 8.5 IR 3 8.5 3 11 3 13 3 15 RDCLK↑ OR 3 8.5 3 11 3 13 3 15 7 16.5 7 19 7 21 7 23 RDCLK↑ AF/AE ns ns WRTCLK↑ WRTCLK↑ UNIT ns 7 17 7 19 7 21 7 23 tPLH tPHL WRTCLK↑ HF 7 15 7 17 7 19 7 21 ns RDCLK↑ HF 7 15.5 7 18 7 20 7 22 ns tPLH RESET low AF/AE 2 9 2 11 2 13 2 15 ns tPHL RESET low HF 2 10 2 12 2 14 2 16 ns ten OE1, OE2 Any Q 2 8.5 2 11 2 11 2 11 ns tdis Any Q 2 OE1, OE2 ‡ This parameter is measured with a 30-pF load (see Figure 6). 9.5 2 11 2 14 2 14 ns 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, TYP f = 5 MHz 53 UNIT pF PARAMETER MEASUREMENT INFORMATION 7V PARAMETER S1 ten 500 Ω From Output Under Test Test Point CL = 50 pF (see Note A) tdis 500 Ω S1 tPZH tPZL tPHZ tPLZ tPLH tPHL tpd Open Closed Open Closed Open Open tw LOAD CIRCUIT 3V Input 0V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V tsu th 3V Data Input 1.5 V 1.5 V 0V 3V Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 1.5 V 0V tPZL 3V 1.5 V 0V tPLH 1.5 V 1.5 V tPZH 1.5 V VOL tPLZ ≈ 3.5 V Output Waveform 1 S1 at 7 V tPHL VOH Output 1.5 V 3V Timing Input Input 1.5 V Output Waveform 2 S1 at Open VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTE A: CL includes probe and jig capacitance. Figure 5. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs LOAD CAPACITANCE SUPPLY CURRENT vs CLOCK FREQUENCY 200 VCC = 5 V TA = 25°C RL = 500 Ω TA = 75°C CL = 0 pF 180 typ + 6 VCC = 5.5 V 160 I CC(f) – Supply Current – mA t pd – Propagation Delay Time – ns typ + 8 typ + 4 typ + 2 typ VCC = 5 V 140 120 100 VCC = 4.5 V 80 60 40 20 0 typ – 2 0 50 100 150 200 250 300 0 20 30 Figure 6 Figure 7 POST OFFICE BOX 655303 40 50 fclock – Clock Frequency – MHz CL – Load Capacitance – pF 12 10 • DALLAS, TEXAS 75265 60 70 SN74ACT7805 256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS201B – MARCH 1991 – REVISED APRIL 1998 APPLICATION INFORMATION SN74ACT7805 WRTCLK RDCLK CLOCK A W/RA WRTEN1 OE1 CSA WRTEN2 RDEN CLOCK B W/RB CSB OE2 18 D0–D17 B0–B17 Q0–Q17 SN74ACT7805 RDCLK WRTCLK OE1 WRTEN1 RDEN WRTEN2 OE2 18 A0–A17 Q0–Q17 D0–D17 Figure 8. Bidirectional Configuration SN74ACT7805 WRTCLK WRTCLK RDCLK WRTEN1 WRTEN1 RDEN WRTEN2 WRTEN2 OE1 IR RDCLK OE1 OR OE2 OE2 36 D0–D35 D0–D17 Q0–Q17 OR IR SN74ACT7805 WRTCLK RDCLK WRTEN1 RDEN WRTEN2 OE1 IR OR OE2 36 D0–D17 Q0–Q17 Q0–Q35 Figure 9. Word-Width Expansion: 256 × 36 Bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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