SN74ACT7806-25DL

SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS438C – APRIL 1992 – REVISED APRIL 1998 D D D D D D D D D D D Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 Words by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable Almost-Full/Almost-Empty Flag Fast Access Times of 15 ns With a 50-pF Load and All Data Outputs Switching Simultaneously Data Rates up to 50 MHz 3-State Outputs Pin-to-Pin Compatible With SN74ACT7804 and SN74ACT7814 Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7806 is a 256-word by 18-bit FIFO for high speed and fast access times. It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format. Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds the number of words clocked out by 256. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. DL PACKAGE (TOP VIEW) RESET D17 D16 D15 D14 D13 D12 D11 D10 VCC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 HF PEN AF/AE LDCK NC NC FULL 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OE Q17 Q16 Q15 GND Q14 VCC Q13 Q12 Q11 Q10 Q9 GND Q8 Q7 Q6 Q5 VCC Q4 Q3 Q2 GND Q1 Q0 UNCK NC NC EMPTY NC – No internal connection Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output is high when the FIFO contains 128 or more words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (256 – Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (255 – Y) words. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright  1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS438C – APRIL 1992 – REVISED APRIL 1998 description (continued) A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, HF low, and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up.The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with respect to the data inputs and are in the high-impedance state when the output-enable (OE) input is high. The SN74ACT7806 is characterized for operation from 0°C to 70°C. logic symbol† Φ FIFO 256 × 18 SN74ACT7806 RESET LDCK UNCK 1 OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 23 21 FULL LDCK 32 56 PEN RESET 25 HALF-FULL UNCK ALMOST FULL/EMPTY EN1 EMPTY 22 24 FULL HF AF/AE 29 EMPTY PROGRAM ENABLE 0 0 33 20 34 19 36 18 37 17 38 16 40 15 41 14 42 12 43 11 45 Data Data 1 9 46 8 47 7 48 6 49 5 51 4 53 3 54 2 55 17 17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS438C – APRIL 1992 – REVISED APRIL 1998 functional block diagram OE D0–D17 Location 1 Location 2 Read Pointer UNCK 256 × 18 SRAM Write Pointer LDCK Location 255 Location 256 Q0 – Q17 EMPTY Reset Logic RESET StatusFlag Logic PEN FULL HF AF/AE Terminal Functions TERMINAL I/O DESCRIPTION 24 O Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or fewer words or (256 – Y) or more words. AF/AE is high after reset. D0–D17 2–9, 11–12, 12–14 I 18-bit data input port EMPTY 29 O Empty flag. EMPTY is high when the FIFO memory is not empty; EMPTY is low when the FIFO memory is empty or upon assertion of RESET. FULL 28 O Full flag. FULL is high when the FIFO memory is not full or upon assertion of RESET; FULL is low when the FIFO memory is full. HF 22 O Half-full flag. HF is high when the FIFO memory contains 128 or more words. HF is low after reset. LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high. OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state. PEN 23 I Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D6 is latched as an AF/AE offset value when PEN is low and WRTCLK is high. Q0–Q17 33–34, 36–38, 40–43, 45–49, 51, 53–55 O 18-bit data output port RESET 1 I Reset. A low level on this input resets the FIFO and drives FULL high and HF and EMPTY low. UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high. NAME NO. AF/AE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS438C – APRIL 1992 – REVISED APRIL 1998 offset values for AF/AE The AF/AE flag has two programmable limits, the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. The AF/AE flag is high when the FIFO contains X or fewer words or (256 – Y) or more words. To program the offset values, PEN can be brought low after reset only when LDCK is low. On the following low-to-high transition of LDCK, the binary value on D0–D6 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LDCK reprograms Y to the binary value on D0–D6 at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are disabled while the offsets are programmed. A maximum value of 127 can be programmed for either X or Y (see Figure 1). To use the default values of X = Y = 32, PEN must be held high. RESET LDCK ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Don’t Care PEN ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÌÌÌÌÌ ÌÌÌÌÌ D0–D6 Don’t Care X and Y Y EMPTY Figure 1. Programming X and Y Separately 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RESET 1 0 PEN ÏÏ ÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏ ÏÏÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ LDCK D0–D17 W1 W2 W (X+1) W128 W (256–Y) Don’t Care W256 1 0 W1 W2 W (Y+1) W (Y+2) W129 W130 W (256–X) W (257–X) W255 W256 EMPTY AF/AE HF Define the AF/AE Flag Using the Default Value of X and Y Figure 2. Write, Read, and Flag Timing Reference 5 SCAS438C – APRIL 1992 – REVISED APRIL 1998 FULL SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY • DALLAS, TEXAS 75265 Q0–Q17 ÏÏ ÏÏ ÏÏ ÏÏ OE ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ POST OFFICE BOX 655303 UNCK SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS438C – APRIL 1992 – REVISED APRIL 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions ’ACT7806-20 VCC VIH Supply voltage VIL IOH Low-level input voltage High-level input voltage Low level output current Low-level TA Operating free-air temperature ’ACT7806-40 MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 2 High-level output current IOL ’ACT7806-25 MIN 2 2 UNIT V V 0.8 0.8 0.8 V Q outputs, flags –8 –8 –8 mA Q outputs 16 16 16 8 8 8 Flags 0 70 0 70 0 70 mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC§ Ci Flags Q outputs TEST CONDITIONS MIN MAX 2.4 UNIT VCC = 4.5 V, VCC = 4.5 V, IOH = –8 mA IOL = 8 mA VCC = 4.5 V, VCC = 5.5 V, IOL = 16 mA VI = VCC or 0 0.5 ±5 µA VCC = 5.5 V, VCC = 5.5 V, VO = VCC or 0 VI = VCC – 0.2 V or 0 ±5 µA VCC = 5.5 V, VI = 0, One input at 3.4 V, Other inputs at VCC or GND f = 1 MHz VO = 0, f = 1 MHz ‡ All typical values are at VCC = 5 V, TA = 25°C. § This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 V 0.5 Co 6 TYP‡ • DALLAS, TEXAS 75265 V 400 µA 1 mA 4 pF 8 pF SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS438C – APRIL 1992 – REVISED APRIL 1998 timing requirements over recommended operating conditions (see Figures 1 through 3) ’ACT7806-20 MIN fclock tw Clock frequency MIN Setup time Hold time MAX ’ACT7806-40 MIN 40 MAX 25 LDCK high or low 7 8 12 UNCK high or low 7 8 12 PEN low 7 8 12 10 10 12 RESET low th ’ACT7806-25 50 Pulse duration tsu MAX D0–D17 before LDCK↑ 5 5 5 PEN before LDCK↑ 5 5 5 LDCK inactive before RESET high 5 6 6 D0–D17 after LDCK↑ 0 0 0 LDCK inactive after RESET high 5 6 6 PEN low after LDCK↑ 3 3 3 PEN high after LDCK↓ 0 0 0 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figures 5 and 6) PARAMETER FROM (INPUT) fmax LDCK or UNCK tpd d tpd‡ tPLH TO (OUTPUT) LDCK↑ Any Q UNCK↑ UNCK↑ Any Q LDCK↑ EMPTY UNCK↑ tPHL EMPTY RESET low LDCK↑ tPLH tpd d tPLH tPHL FULL UNCK↑ FULL RESET low LDCK↑ AF/AE UNCK↑ ’ACT7806-20 TYP† MAX ’ACT7806-25 MIN MIN 50 40 9 6 11.5 MAX ’ACT7806-40 MIN MAX 25 MHz 20 9 22 9 24 15 6 18 6 20 10.5 6 15 6 17 6 19 6 15 6 17 6 19 4 16 4 18 4 20 6 15 6 17 6 19 6 15 6 17 6 19 4 18 4 20 4 22 7 18 7 20 7 22 7 18 7 20 7 22 AF/AE 2 10 2 12 2 14 LDCK↑ HF 5 18 5 20 5 22 7 18 7 20 7 22 3 12 3 14 3 16 UNCK↑ HF ns ns RESET low RESET low UNIT ns ns ns ns ns ns ten OE Any Q 2 9 2 10 2 11 ns tdis OE Any Q 2 10 2 11 2 12 ns † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter is measured at CL = 30 pF (see Figure 4). operating characteristics, VCC = 5 V, TA = 25°CFigure 2 PARAMETER Cpd Power dissipation capacitance per FIFO channel POST OFFICE BOX 655303 TEST CONDITIONS Outputs enabled • DALLAS, TEXAS 75265 CL = 50 pF, f = 5 MHz TYP 53 UNIT pF 7 SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS438C – APRIL 1992 – REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION 7V PARAMETER S1 ten 500 Ω From Output Under Test tdis Test Point CL = 50 pF (see Note A) tpd 500 Ω S1 tPZH tPZL tPHZ tPLZ tPLH tPHL Open Closed Open Closed Open Open tw LOAD CIRCUIT 3V Input 0V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V tsu th 3V Data Input 1.5 V 1.5 V 0V 3V Output Control tPZL 3V 1.5 V 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V tPZH 1.5 V VOL Output Waveform 2 S1 at Open VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTE A: CL includes probe and jig capacitance. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 tPLZ ≈ 3.5 V Output Waveform 1 S1 at 7 V tPHL VOH 8 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.5 V 3V Timing Input Input 1.5 V • DALLAS, TEXAS 75265 SN74ACT7806 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS438C – APRIL 1992 – REVISED APRIL 1998 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs LOAD CAPACITANCE SUPPLY CURRENT vs CLOCK FREQUENCY 200 VCC = 5 V TA = 25°C RL = 500 Ω TA = 75°C CL = 0 pF 180 typ + 6 VCC = 5.5 V 160 I CC(f) – Supply Current – mA t pd – Propagation Delay Time – ns typ + 8 typ + 4 typ + 2 typ VCC = 5 V 140 120 100 VCC = 4.5 V 80 60 40 20 0 typ – 2 0 50 100 150 200 250 0 300 10 20 30 40 50 60 70 fclock – Clock Frequency – MHz CL – Load Capacitance – pF Figure 4 Figure 5 APPLICATION INFORMATION LDCK SN74ACT7806 LDCK UNCK FULL EMPTY FULL OE D18–D35 D0–D17 Q0–Q17 UNCK EMPTY OE Q18–Q35 SN74ACT7806 LDCK UNCK FULL EMPTY OE D0–D17 D0–D17 Q0–Q17 Q0–Q17 Figure 6. Word-Width Expansion: 256 × 36 Bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74ACT7806-20DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ACT7806-20 SN74ACT7806-40DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ACT7806-40 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of