SN74AHC08PWR

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN74AHC08, SN54AHC08 SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 SNx4AHC08 Quadruple 2-Input Positive-AND Gates 1 Features 3 Description • • The SNx4AHC08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic. 1 • 2-V to 5.5-V Operating Range Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Device Information(1) PART NUMBER 2 Applications • • • • SN74AHC08 Servers Network Switches PCs and Notebooks Electronic Points of Sale SN54AHC08 PACKAGE BODY SIZE (NOM) SOIC (14) 8.65 mm × 3.90 mm SSOP (14) 6.20 mm × 5.30 mm TVSOP (14) 3.60 mm × 4.40 mm PDIP (14) 19.30 mm × 6.35 mm SO (14) 10.30 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm VQFN (14) 3.50 mm × 3.50 mm LCCC (20) 8.89 mm × 8.89 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic A B Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AHC08, SN54AHC08 SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 1 1 1 2 3 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics, TA = 25°C ........................ 5 Electrical Characteristics, TA = –55°C to 125°C, SN54AHC08............................................................... 6 7.7 Electrical Characteristics, TA = –40°C to 125°C, SN74AHC08............................................................... 6 7.8 Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ 6 7.9 Switching Characteristics, VCC = 5 V ± 0.5 V ........... 7 7.10 Noise Characteristics, SN74AHC08 ....................... 7 7.11 Operating Characteristics........................................ 7 7.12 Typical Characteristics ............................................ 7 8 9 Parameter Measurement Information .................. 8 Detailed Description .............................................. 9 9.1 9.2 9.3 9.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 9 9 9 9 10 Application and Implementation........................ 10 10.1 Application Information.......................................... 10 10.2 Typical Application ............................................... 10 11 Power Supply Recommendations ..................... 11 12 Layout................................................................... 11 12.1 Layout Guidelines ................................................. 11 12.2 Layout Example .................................................... 12 13 Device and Documentation Support ................. 13 13.1 13.2 13.3 13.4 13.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 13 13 13 13 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (May 2013) to Revision J • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Revision H (March 1996) to Revision I Page • Changed document format .................................................................................................................................................... 1 • Extended operating temperature range to 125°C................................................................................................................... 5 2 Submit Documentation Feedback Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 SN74AHC08, SN54AHC08 www.ti.com SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 5 Device Comparison Table PART NUMBER PACKAGE BODY SIZE (NOM) SN74AHC08D SOIC (14) 8.65 mm × 3.90 mm SN74AHC08DB SSOP (14) 6.20 mm × 5.30 mm SN74AHC08DGV TVSOP (14) 3.60 mm × 4.40 mm SN74AHC08N PDIP (14) 19.30 mm × 6.35 mm SN74AHC08NS SO (14) 10.30 mm × 5.30 mm SN74AHC08PW TSSOP (14) 5.00 mm × 4.40 mm SN74AHC08RGY VQFN (14) 3.50 mm × 3.50 mm SN54AHC08FK LCCC (20) 8.89 mm × 8.89 mm 6 Pin Configuration and Functions D, DB, DGV, N, NS, PW, or W Package 14-Pin SOIC, SSOP, TVSOP, PDIP, SO, or TSSOP Top View 13 3 12 4 11 5 10 6 9 7 8 1B 1Y 2A 2B 2Y VCC 2 VCC 4B 4A 4Y 3B 3A 3Y 1 14 2 13 4B 3 12 4A 4Y 4 11 5 10 3B 9 3A 6 7 8 3Y 14 1A 1 GND 1A 1B 1Y 2A 2B 2Y GND RGY Package 14-Pin VQFN Top View 1B 1A NC VCC 4B FK Package 20-Pin LCCC Top View 3 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1Y NC 2A NC 2B NC – No internal connection Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 Submit Documentation Feedback 3 SN74AHC08, SN54AHC08 SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 www.ti.com Pin Functions PIN SOIC, SSOP, TVSOP, PDIP, SO, TSSOP VQFN LCCC 1A 1 1 2 I 1A Input 1B 2 2 3 I 1B Input 1Y 3 3 4 O 1Y Output 2A 4 4 6 I 2A Input 2B 5 5 8 I 2B Input 2Y 6 6 9 O 2Y Output 3Y 8 8 12 O 3Y Output NAME I/O DESCRIPTION 3A 9 9 13 I 3A Input 3B 10 10 14 I 3B Input 4Y 11 11 16 O 4Y Output 4A 12 12 18 I 4A Input 4B 13 13 19 I 4B Input GND 7 7 10 — Ground Pin NC — — 1, 5, 7, 11, 15, 17 — No Connection VCC 14 14 20 — Power Pin 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage –0.5 7 V VI Input voltage (2) –0.5 7 V VO Output voltage, VO (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 -20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND ±50 mA TJ Junction temperature 150 °C Tstg Storage temperature 150 °C (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Submit Documentation Feedback Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 SN74AHC08, SN54AHC08 www.ti.com SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 7.3 Recommended Operating Conditions (1) See VCC Supply voltage VCC= 2 V VIH High-level input voltage MIN MAX 2 5.5 VCC= 3V 2.1 V 3.85 VCC= 2 V Low-level Input voltage V 1.5 VCC= 5.5 V VIL UNIT 0.5 VCC= 3 V 0.9 VCC= 5.5 V V 1.65 VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC= 2 V IOH High-level output current IOL Low-level output current Δt/Δv Input Transition rise or fall rate TA Operating free-air temperature (1) –50 VCC= 3.3 V ± 0.3 V –4 VCC= 5 V ± 0.5 V –8 VCC= 2 V 50 VCC= 3.3 V ± 0.3 V 4 VCC= 5 V ± 0.5 V 8 VCC= 3.3 V ± 0.3 V mA mA 100 VCC= 5 V ± 0.5 V ns/V 20 SN54AHC08 –55 125 SN74AHC08 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 7.4 Thermal Information SN74AHC08 THERMAL METRIC (1) RθJA (1) D (SOIC) DB (SSOP) DGV (TVSOP) N (PDIP) NS (SO) PW (TSSOP) RGY (VQFN) 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 86 96 127 80 76 113 47 Junction-to-ambient thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics, TA = 25°C over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VCC MIN TYP 2V 1.9 2 3V 2.9 3 4.5 V 4.4 4.5 IOH = –4 mA 3V 2.58 IOH = –8 mA 4.5 V 3.94 VOH IOL = 50 µA VOL IOH = 4 mA IOH = 8 mA II VI = 5.5 V or GND ICC VI = VCC or GND, Ci VI = VCC or GND IO = 0 MAX UNIT V 2V 0.1 3V 0.1 4.5 V 0.1 3V 0.36 4.5 V 0.36 0 V to 5.5 V ±0.1 µA 2 µA 10 pF 5.5 V 5V Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 4 Submit Documentation Feedback V 5 SN74AHC08, SN54AHC08 SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 www.ti.com 7.6 Electrical Characteristics, TA = –55°C to 125°C, SN54AHC08 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH MIN 2V 1.9 3V 2.9 4.5 V 4.4 IOH = –4 mA 3V 2.48 IOH = –8 mA 4.5 V 3.8 MAX 0.1 3V 0.1 4.5 V 0.1 IOH = 4 mA 3V 0.5 IOH = 8 mA 4.5 V 0.5 VOL II VI = 5.5 V or GND ICC VI = VCC or GND, Ci VI = VCC or GND 0 V to 5.5 V IO = 0 UNIT V 2V IOL = 50 µA (1) VCC 5.5 V V ±1 (1) µA 20 µA 5V pF On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. 7.7 Electrical Characteristics, TA = –40°C to 125°C, SN74AHC08 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH VCC TA MIN 2V 1.9 3V 2.9 4.5 V 4.4 IOH = –4 mA 3V 2.48 IOH = –8 mA 4.5 V 3.8 IOL = 50 µA MAX V 2V 0.1 3V 0.1 4.5 V VOL 0.1 TA = –40°C to 85°C 0.44 V IOH = 4 mA 3V TA = –40°C to125°C Recommended 0.5 TA = –40°C to 85°C 0.44 IOH = 8 mA 4.5 V TA = –40°C to125°C Recommended 0.5 II VI = 5.5 V or GND ICC VI = VCC or GND, IO = 0 Ci VI = VCC or GND UNIT 0 V to 5.5 V ±1 µA 5.5 V 20 µA 10 pF 5V TA = –40°C to 85°C 7.8 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA MIN A or B Y CL = 15 pF 6.2 (1) 8.8 (1) 1 (1) 10.5 (1) TA = –40°C to 85°C, SN74AHC08 1 10.5 TA = –40°C to 125°C Recommended, SN74AHC08 1 10.5 TA = 25°C tPLH, tPHL (1) 6 A or B Y CL = 50 pF MAX TA = –55°C to 125°C, SN54AHC08 TA = 25°C tPLH, tPHL TYP 8.7 12.3 TA = –55°C to 125°C, SN54AHC08 1 14 TA = –40°C to 85°C, SN74AHC08 1 14 TA = –40°C to 125°C Recommended, SN74AHC08 1 14 UNIT ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. Submit Documentation Feedback Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 SN74AHC08, SN54AHC08 www.ti.com SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 7.9 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA MIN TA = 25°C tPLH, tPHL A or B Y CL = 15 pF TYP MAX (1) (1) 4.3 1 (1) 7 (1) TA = –40°C to 85°C, SN74AHC08 1 7 TA = –40°C to 125°C Recommended, SN74AHC08 1 7 TA = 25°C tPLH, tPHL (1) A or B Y CL = 50 pF 5.9 TA = –55°C to 125°C, SN54AHC08 5.8 7.9 TA = –55°C to 125°C, SN54AHC08 1 9 TA = –40°C to 85°C, SN74AHC08 1 9 TA = –40°C to 125°C Recommended, SN74AHC08 1 9 UNIT ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. 7.10 Noise Characteristics, SN74AHC08 VCC = 5 V, CL = 50 pF, TA = 25°C (1) MIN MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.4 VIH(D) High-level dynamic input voltage 3.5 VIL(D) Low-level dynamic input voltage (1) V V 1.5 V Characteristics are for surface-mount packages only. 7.11 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, f = 1 MHz TYP UNIT 18 pF 7.12 Typical Characteristics VCC = 5.5 V Figure 1. AHC Family VOL vs IOL Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 Submit Documentation Feedback 7 SN74AHC08, SN54AHC08 SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 www.ti.com 8 Parameter Measurement Information VCC From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC 50% VCC Input 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL VOH 50% VCC VOL 50% VCC tPHL Out-of-Phase Output Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 SN74AHC08, SN54AHC08 www.ti.com SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 9 Detailed Description 9.1 Overview The SNx4AHC08 devices are quadruple 2-input positive-AND gates with low drive that will produce slow rise and fall times. This slow transition reduces ringing on the output signal. The inputs are high impedance when VCC = 0 V. 9.2 Functional Block Diagram A Y B 9.3 Feature Description Slow rise and fall time on outputs allow for low-noise outputs. 9.4 Device Functional Modes Table 1 is the function table for the SNx4AHC08. Table 1. Function Table (Each Gate) INPUTS A B OUTPUT Y H H H L X L X L L Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 Submit Documentation Feedback 9 SN74AHC08, SN54AHC08 SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information A common application for AND gates is the use in power sequencing. Power sequencing is often employed in applications that require a processor or other delicate device with specific voltage timing requirements in order to protect the device from malfunctioning. Using the SN74AHC08 to verify that the processor has turned on can protect it from harmful signals. 10.2 Typical Application VCC = 5 V A Y MCU (MSP43x) B Temp. EN Sensor VO Figure 3. Typical Application Diagram 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions must be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended input conditions – Rise time and fall time specs: See (Δt/Δv) in the Recommended Operating Conditions table. – Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC 2. Recommend output conditions – Load currents should not exceed 25 mA per output and 50 mA total for the part – Outputs should not be pulled above VCC 10 Submit Documentation Feedback Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 SN74AHC08, SN54AHC08 www.ti.com SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 Typical Application (continued) 10.2.3 Application Curve VCC = 5.5 V Figure 4. AHC Family VOH vs IOH 11 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Absolute Maximum Ratings table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 5 are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled. Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 Submit Documentation Feedback 11 SN74AHC08, SN54AHC08 SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 www.ti.com 12.2 Layout Example Vcc Unused Input Input Output Output Unused Input Input Figure 5. Layout Diagram 12 Submit Documentation Feedback Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 SN74AHC08, SN54AHC08 www.ti.com SCLS236J – MARCH 1996 – REVISED DECEMBER 2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54AHC08 Click here Click here Click here Click here Click here SN74AHC08 Click here Click here Click here Click here Click here 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1996–2015, Texas Instruments Incorporated Product Folder Links: SN74AHC08 SN54AHC08 Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9682001Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629682001Q2A SNJ54AHC 08FK SN74AHC08D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC08 SN74AHC08DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA08 SN74AHC08DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC08 SN74AHC08DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA08 SN74AHC08DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC08 SN74AHC08DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC08 SN74AHC08N ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 125 SN74AHC08N SN74AHC08NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC08 SN74AHC08PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA08 SN74AHC08PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA08 SN74AHC08PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 HA08 SN74AHC08PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA08 SN74AHC08PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA08 SN74AHC08RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HA08 SNJ54AHC08FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629682001Q2A SNJ54AHC Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2018 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 08FK (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of