SN74AHC123ADR

 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 D Operating Range 2-V to 5.5-V VCC D Schmitt-Trigger Circuitry On A, B, and CLR SN54AHC123A . . . J OR W PACKAGE SN74AHC123A . . . D, DB, DGV, N, OR PW PACKAGE (TOP VIEW) Inputs for Slow Input Transition Rates D Edge Triggered From Active-High or D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A SN54AHC123A . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC 1R ext /C ext D D D D 1A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext GND Active-Low Gated Logic Inputs Retriggerable for Very Long Output Pulses Overriding Clear Terminates Output Pulse Glitch-Free Power-Up Reset On Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information The ’AHC123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation. 1CLR 1Q NC 2Q 2Cext 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Cext 1Q NC 2Q 2CLR 2R ext /Cext GND NC 2A 2B These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. 4 NC − No internal connection ORDERING INFORMATION PDIP − N −55°C 125°C −55 C to 125 C TOP-SIDE MARKING Tube SN74AHC123AN Tube SN74AHC123AD Tape and reel SN74AHC123ADR SSOP − DB Tape and reel SN74AHC123ADBR HA123A TSSOP − PW Tape and reel SN74AHC123APWR HA123A TVSOP − DGV Tape and reel SN74AHC123ADGVR HA123A CDIP − J Tube SNJ54AHC123AJ SNJ54AHC123AJ CFP − W Tube SNJ54AHC123AW SNJ54AHC123AW LCCC − FK Tube SNJ54AHC123AFK SNJ54AHC123AFK SOIC − D −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SN74AHC123AN AHC123A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated    !" # $%&" !#  '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+  '*%$"# $')!" " 121 3  !)) '!!&"&# !& "&#"&* %)&## ",&.#& "&*+  !)) ",& '*%$"# '*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 description/ordering information (continued) The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR input can be used to override A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing. The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’AHC123A is shown in Figure 10. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 6. During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse. For additional application information on multivibrators, see the application report Designing With the SN74AHC123A and SN74AHCT123A, literature number SCLA014. FUNCTION TABLE (each multivibrator) INPUTS OUTPUTS CLR A B Q Q L X X X H X L L† H H† X X L L† H† H L ↑ H # H ↑ L H † These outputs are based on the assumption that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the setup. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 logic diagram, each multivibrator (positive logic) Rext/Cext A Cext B Q CLR R Q input/output timing diagram trr A B CLR Rext/Cext Q Q tw tw POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tw + trr 3 
 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range in high or low state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to the network ground terminal. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54AHC123A VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 3 V VCC = 5.5 V VCC = 2 V SN74AHC123A MIN MAX MIN MAX 2 5.5 2 5.5 1.5 V 1.5 2.1 2.1 3.85 3.85 VCC = 3 V VCC = 5.5 V UNIT V 0.5 0.5 0.9 0.9 VIL Low-level input voltage VI VO Input voltage 0 5.5 0 5.5 V Output voltage 0 VCC −50 0 VCC −50 V IOH High-level output current 1.65 VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 2 V IOL Rext ∆t/∆VCC TA Low-level output current External timing resistance VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 2 V VCC > 3 V Power-up ramp rate 1.65 −4 −4 −8 −8 50 50 4 4 8 8 5k 5k 1k 1k 1 Operating free-air temperature −55 −40 mA mA mA mA Ω 1 125 V ms/V 85 °C NOTE 4: Unused Rext/Cext terminals should be left unconnected. All remaining unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −4 mA IOH = −8 mA II ICC ICC SN74AHC123A 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 3V 2.58 2.48 2.48 4.5 V 3.94 IOL = 50 mA VOL SN54AHC123A MIN IOH = −50 mA VOH TA = 25°C TYP MAX VCC MIN MAX 3.8 MIN MAX V 3.8 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 IOL = 4 mA IOL = 8 mA 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 Rext/Cext† VI = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 A, B, and CLR VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1 Quiescent VI = VCC or GND, Active state (per circuit) IO = 0 VI = VCC or GND, Rext/Cext = 0.5 VCC 5.5 V UNIT 4 40 40 3V 160 250 280 280 4.5 V 280 500 650 650 5.5 V 360 750 975 975 Ci VI = VCC or GND 5V 1.9 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. † This test is performed with the terminal in the off-state condition. 10 V mA A mA mA pF timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS TA = 25°C MIN TYP MAX SN54AHC123A MIN MAX SN74AHC123A MIN CLR 5 5 5 A or B trigger Rext = 1 kΩ, Cext = 100 pF 5 ‡ 76 5 ‡ 5 ‡ Rext = 1 kΩ, Cext = 0.01 mF ‡ 1.8 ‡ ‡ tw Pulse duration trr Pulse retrigger time MAX UNIT ns ns ms ‡ See retriggering data in the application information section. timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS MIN TA = 25°C TYP MAX SN54AHC123A MIN MAX SN74AHC123A MIN CLR 5 5 5 A or B trigger 5 ‡ 59 5 ‡ 5 ‡ 1.5 ‡ ‡ tw Pulse duration trr Pulse retrigger time Rext = 1 kΩ, Cext = 100 pF Rext = 1 kΩ, Cext = 0.01 mF ‡ See retriggering data in the application information section. POST OFFICE BOX 655303 ‡ • DALLAS, TEXAS 75265 MAX UNIT ns ns ms 5 
 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS tPLH tPHL A or B Q or Q CL = 15 pF tPLH tPHL CLR Q or Q CL = 15 pF tPLH tPHL CLR trigger Q or Q CL = 15 pF tPLH tPHL A or B Q or Q CL = 50 pF tPLH tPHL CLR Q or Q CL = 50 pF tPLH tPHL CLR trigger Q or Q CL = 50 pF Q or Q CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ tw† ∆tw‡ MIN TA = 25°C TYP MAX MAX MIN MAX 9.5* 20.6* 1* 24* 1 24 20.6* 1* 24* 1 24 7.5* 15.8* 1* 18.5* 1 18.5 9.3* 15.8* 1* 18.5* 1 18.5 10* 22.4* 1* 26* 1 26 10.6* 22.4* 1* 26* 1 26 10.5 24.1 1 27.5 1 27.5 11.8 24.1 1 27.5 1 27.5 8.9 19.3 1 22 1 22 10.5 19.3 1 22 1 22 11 25.9 1 29.5 1 29.5 12.3 25.9 1 29.5 1 29.5 182 240 90 100 110 90 110 0.9 1 1.1 0.9 1.1 ±1 POST OFFICE BOX 655303 SN74AHC123A MIN 10.2* * On products compliant to MIL-PRF-38535, this parameter is not production tested. † tw = Pulse duration at Q and Q outputs ‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package 6 SN54AHC123A • DALLAS, TEXAS 75265 300 UNIT ns ns ns ns ns ns 300 ns 90 110 ms 0.9 1.1 ms % 
 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (NPUT) TO (OUTPUT) TEST CONDITIONS tPLH tPHL A or B Q or Q CL = 15 pF tPLH tPHL CLR Q or Q CL = 15 pF tPLH tPHL CLR trigger Q or Q CL = 15 pF tPLH tPHL A or B Q or Q CL = 50 pF tPLH tPHL CLR Q or Q CL = 50 pF tPLH tPHL CLR trigger Q or Q CL = 50 pF Q or Q CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ tw† ∆tw‡ MIN TA = 25°C TYP MAX SN54AHC123A SN74AHC123A MIN MAX MIN MAX 6.5* 12* 1* 14* 1 14 7.1* 12* 1* 14* 1 14 5.3* 9.4* 1* 11* 1 11 6.5* 9.4* 1* 11* 1 11 6.9* 12.9* 1* 15* 1 15 7.4* 12.9* 1* 15* 1 15 7.3 14 1 16 1 16 8.3 14 1 16 1 16 6.3 11.4 1 13 1 13 7.4 11.4 1 13 1 13 7.6 14.9 1 17 1 17 8.7 14.9 1 17 1 17 167 200 90 100 110 90 110 0.9 1 1.1 0.9 1.1 240 UNIT ns ns ns ns ns ns 240 ns 90 110 ms 0.9 1.1 ms ±1 % * On products compliant to MIL-PRF-38535, this parameter is not production tested. † tw = Pulse duration at Q and Q outputs ‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 29 UNIT pF 7 
 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point tw CL (see Note A) VCC Inputs or Outputs 50% VCC 50% VCC 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATION VCC Input A (see Note B) 50% VCC 0V VCC Input B (see Note B) 50% VCC 50% VCC 0V 50% VCC VOH In-Phase Output 50% VCC In-Phase Output VOL VOH VOL 50% VCC Out-of-Phase Output 50% VCC VOLTAGE WAVEFORMS DELAY TIMES VOLTAGE WAVEFORMS DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: ZO = 50 Ω, tr + 3 ns, tf + 3 ns. C. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VOH 50% VCC VOL tPLH tPHL tPHL 50% VCC tPHL tPLH 0V tPLH Out-of-Phase Output VCC Input CLR (see Note B) VOH 50% VCC VOL 
 
    
 
SCLS352H − JULY 1997 − REVISED OCTOBER 2005 APPLICATION INFORMATION caution in use To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep the wiring between the external components and Cext and Rext/Cext terminals as short as possible. power-down considerations Large values of Cext can cause problems when powering down the ’AHC123A devices because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor can discharge from VCC through the protection diodes at pin 2 or pin 14. Current through the input protection diodes must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than t = VCC × Cext/30 mA. For example, if VCC = 5 V and Cext = 15 pF, the VCC supply must turn off no faster than t = (5 V) × (15 pF)/30 mA = 2.5 ns. Usually, this is not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero occurs, the ’AHC123A devices can sustain damage. To avoid this possibility, use external clamping diodes. output pulse duration The output pulse duration, tw, is determined primarily by the values of the external capacitance (CT) and timing resistance (RT). The timing components are connected as shown in Figure 2. VCC RT CT To Rext/Cext Terminal To Cext Terminal Figure 2. Timing-Component Connections The pulse duration is given by: tw + K RT CT (1) if CT is ≥1000 pF, K = 1.0 or if CT is