SN74AHC16373DGGR

SN54AHC16373, SN74AHC16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS329G – MARCH 1996 – REVISED JANUARY 2000 D D D D D D D D Members of the Texas Instruments Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V VCC Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings SN54AHC16373 . . . WD PACKAGE SN74AHC16373 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE description The ’AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AHC16373 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AHC16373 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright  2000, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHC16373, SN74AHC16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS329G – MARCH 1996 – REVISED JANUARY 2000 FUNCTION TABLE (each 8-bit latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 1EN 48 C3 24 2EN 25 C4 47 3D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1LE 1D1 1 2OE 48 47 2LE C1 2 1D 1Q1 24 25 C1 2D1 36 To Seven Other Channels To Seven Other Channels 2 POST OFFICE BOX 655303 1D • DALLAS, TEXAS 75265 13 2Q1 SN54AHC16373, SN74AHC16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS329G – MARCH 1996 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54AHC16373 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 3 V VCC = 5.5 V VCC = 2 V VIL VI VO IOH Low-level input voltage Output voltage VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 2 V IOL ∆t/∆v Low-level output current Input transition rise or fall rate MAX 2 5.5 1.5 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V SN74AHC16373 MIN MAX 2 5.5 UNIT V 1.5 2.1 2.1 3.85 3.85 0.5 VCC = 3 V VCC = 5.5 V Input voltage High-level output current MIN V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC –50 0 VCC –50 mA –4 –4 –8 –8 50 50 4 4 8 8 100 100 20 20 V mA mA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHC16373, SN74AHC16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS329G – MARCH 1996 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 mA VOH IOH = –4 mA IOH = –8 mA IOL = 50 mA VOL IOL = 4 mA IOL = 8 mA II IOZ ICC Ci VI = VCC or GND VO = VCC or GND, VI = VIL or VIH VI = VCC or GND, VI = VCC or GND IO = 0 VCC MIN TA = 25°C TYP MAX SN54AHC16373 MIN MAX SN74AHC16373 MIN 2V 1.9 1.9 1.9 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 3V 2.58 2.48 2.48 4.5 V 3.94 3.8 MAX UNIT V 3.8 2V 0.1 0.1 0.1 0.1 3V 0.1 0.1 4.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 V 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ±0.1 ±1* ±1 mA 5.5 V ±0.25 ±2.5 ±2.5 mA 4 40 40 mA 10 pF 5.5 V 5V 2.5 10 Co VO = VCC or GND 5V 4 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. pF timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX SN54AHC16373 MIN MAX SN74AHC16373 MIN MAX UNIT tw Pulse duration, LE high 5 5 5 ns tsu Setup time, data before LE↓ 4 4 4 ns th Hold time, data after LE↓ 1 1 1 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX MIN MAX SN74AHC16373 MIN MAX UNIT tw Pulse duration, LE high 5 5 5 ns tsu Setup time, data before LE↓ 4 4 4 ns th Hold time, data after LE↓ 1 1 1 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN54AHC16373 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHC16373, SN74AHC16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS329G – MARCH 1996 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL D Q CL = 15 pF tPLH tPHL LE Q CL = 15 pF tPZH tPZL OE Q CL = 15 pF tPHZ tPLZ OE Q CL = 15 pF tPLH tPHL D Q CL = 50 pF tPLH tPHL LE Q CL = 50 pF tPZH tPZL OE Q CL = 50 pF tPHZ tPLZ OE Q CL = 50 pF tsk(o) MIN TA = 25°C TYP MAX SN54AHC16373 SN74AHC16373 MIN MAX MIN MAX 7.3* 13* 1* 15* 1 15 7.3* 13* 1* 15* 1 15 7* 13* 1* 15* 1 15 7* 13* 1** 15* 1 15 7.3* 13* 1* 15* 1 15 7.3* 13* 1* 15* 1 15 10* 14* 1* 16* 1 16 10* 14* 1* 16* 1 16 9.8 14 1 16 1 16 9.8 14 1 16 1 16 9.5 14.5 1 16.5 1 16.5 9.5 14.5 1 16.5 1 16.5 9.3 14.9 1 16 1 16 8 14.9 1 16 1 16 10.4 15.5 1 17 1 17 11.6 15.5 1 17 1 17 1.5** CL = 50 pF 1.5 UNIT ns ns ns ns ns ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL D Q CL = 15 pF tPLH tPHL LE Q CL = 15 pF tPZH tPZL OE Q CL = 15 pF tPHZ tPLZ OE Q CL = 15 pF tPLH tPHL D Q CL = 50 pF tPLH tPHL LE Q CL = 50 pF tPZH tPZL OE Q CL = 50 pF tPHZ tPLZ OE Q CL = 50 pF tsk(o) TA = 25°C MIN TYP MAX SN54AHC16373 SN74AHC16373 MIN MAX MIN MAX 5* 8.2* 1* 9.5* 1 9.5 5* 8.2* 1* 9.5* 1 9.5 4.9* 8.5* 1* 9.5* 1 9.5 4.9* 8.5* 1* 9.5* 1 9.5 5.5* 9.1* 1* 10* 1 10 5.5* 9.1* 1* 10* 1 10 5* 9.5* 1* 10* 1 10 5* 9.5* 1* 10* 1 10 6.5 9.2 1 10.5 1 10.5 6.5 9.2 1 10.5 1 10.5 6.4 9.5 1 10.5 1 10.5 6.4 9.5 1 10.5 1 10.5 6 10.1 1 11.5 1 11.5 6 10.1 1 11.5 1 11.5 6.5 10.5 1 11.5 1 11.5 7.5 10.5 1** 1 11.5 1 11.5 CL = 50 pF 1 UNIT ns ns ns ns ns ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54AHC16373, SN74AHC16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS329G – MARCH 1996 – REVISED JANUARY 2000 noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHC16373 PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.34 0.8 V Quiet output, minimum dynamic VOL –0.1 –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.6 High-level dynamic input voltage V 3.5 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V 1.5 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 21 pF SN54AHC16373, SN74AHC16373 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS329G – MARCH 1996 – REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AHC16373DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC16373 SN74AHC16373DGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HE373 SN74AHC16373DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC16373 SN74AHC16373DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHC16373 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of