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SN74AHC1G08
SCLS314P – MARCH 1996 – REVISED MARCH 2016
SN74AHC1G08 Single 2-Input Positive-AND Gate
1 Features
3 Description
•
•
•
•
•
The SN74AHC1G08 device is a single 2-input
positive-AND gate. The device performs the Boolean
function Y = A ● B or Y = A + B in positive logic.
1
•
•
Operating Range 2 V to 5.5 V
Maximum tpd of 7 ns at 5 V
Low Power Consumption, 10-μA Maximum ICC
±8-mA Output Drive at 5 V
Schmitt-Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AHC1G08DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74AHC1G08DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74AHC1G08DRL
SOT (5)
1.60 mm × 1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
B
1
2
4
Y
Barcode Scanners
Cable Solutions
E-Books
Embedded PCs
Field Transmitter: Temperature or Pressure
Sensors
Fingerprint Biometrics
HVAC: Heating, Ventilating, and Air Conditioning
Network-Attached Storage (NAS)
Server Motherboard and PSU
Software Defined Radios (SDR)
TV: High Definition (HDTV), LCD, and Digital
Video Communications Systems
Wireless Data Access Cards, Headsets,
Keyboards, Mice, and LAN Cards
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G08
SCLS314P – MARCH 1996 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application ................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 11
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (June 2015) to Revision P
•
Page
Changed VIL max value on Recommended Operating Conditions table from 5.5 V to 0.5 V ................................................ 4
Changes from Revision N (November 2012) to Revision O
Page
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Added Applications ................................................................................................................................................................. 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added ESD Ratings table....................................................................................................................................................... 4
•
Added Thermal Information table. .......................................................................................................................................... 5
Changes from Revision M (June 2005) to Revision N
•
2
Page
Changed document format from Quicksilver to DocZone. ..................................................................................................... 1
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SCLS314P – MARCH 1996 – REVISED MARCH 2016
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
A
1
B
2
GND
3
5
V CC
4
Y
DCK Package
5-Pin SC70
Top View
A
1
B
2
GND
3
5
V CC
4
Y
DRL Package
5-Pin SOT
Top View
A
1
B
2
GND
5
V CC
4
Y
See mechanical drawings for dimensions (in Mechanical, Packaging, and Orderable Information).
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
A
I
Data Input
2
B
I
Data Input
3
GND
—
Ground
4
Y
O
Data Output
5
VCC
—
Power
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SCLS314P – MARCH 1996 – REVISED MARCH 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 3 V
VCC = 5.5 V
MIN
MAX
2
5.5
Low-level Input voltage
V
1.5
2.1
V
3.85
VCC = 2 V
VIL
UNIT
0.5
VCC = 3 V
0.9
VCC = 5.5 V
V
1.65
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
–50
µA
IOH
High-level output current
VCC = 2 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
VCC = 3.3 V ± 0.3 V
–4
VCC = 5 V ± 0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ± 0.3 V
4
VCC = 5 V ± 0.5 V
8
VCC = 3.3 V ± 0.3 V
100
VCC = 5 V ± 0.5 V
20
–55
125
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74AHC1G08
THERMAL METRIC (1)
RθJA
(1)
DBV (SOT-23)
DCK (SC70)
DRL (SOT)
5 PINS
5 PINS
5 PINS
206
252
142
Junction-to-ambient thermal resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
IOH = –50 µA
VOH
TA = –55°C to 125°C
MIN
TYP
MAX
MIN
2V
1.9
2
1.9
3V
2.9
3
2.9
4.5
4.5 V
4.4
IOH = –4 mA
3V
2.58
2.48
IOH = –8 mA
4.5 V
3.94
3.8
MAX
4.4
UNIT
V
2V
0.1
0.1
3V
0.1
0.1
4.5 V
0.1
0.1
IOL = 4 mA
3V
0.36
0.44
IOL = 8 mA
4.5 V
0.36
0.44
0 V to 5.5 V
±0.1
±1
µA
1
10
µA
10
10
pF
IOL = 50 µA
VOL
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
Ci
VI = VCC or GND
IO = 0
5.5 V
5V
4
V
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
OUTPUT
(OUTPUT) CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
MIN
TA = –40°C to 85°C
TA = –55°C to
125°C
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
6.2
8.8
1
10.5
1
11
6.2
8.8
1
10.5
1
11
8.7
12.3
1
14
1
14.5
8.7
12.3
1
14
1
14.5
ns
ns
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
OUTPUT
(OUTPUT) CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
MIN
TA = –40°C to 85°C
TA = –55°C to
125°C
TYP
MAX
MIN
MAX
MIN
MAX
4.3
5.9
1
7
1
7.5
4.3
5.9
1
7
1
7.5
5.8
7.9
1
9
1
9.5
5.8
7.9
1
9
1
9.5
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UNIT
ns
ns
5
SN74AHC1G08
SCLS314P – MARCH 1996 – REVISED MARCH 2016
www.ti.com
6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
TYP
f = 1 MHz
18
UNIT
pF
6.9 Typical Characteristics
5
Signal Voltage (V)
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
50
Time (ns)
C001
Figure 1. Response Time vs Output Voltage (TA = 25°C, VA = 5 V)
6
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7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
0V
th
VCC
50% VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
50% VCC
VOH
50% VCC
VOL
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
VCC
Output
Control
50% VCC
50% VCC
VOH
0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74AHC1G08 device is a single 2-input positive-AND gate. The device performs the Boolean function Y =
A ● B or Y = A + B in positive logic.
8.2 Functional Block Diagram
A
B
1
4
2
Y
Figure 3. Logic Diagram (Positive Side)
8.3 Feature Description
The SN74AHC1G08 device has a wide operating VCC range of 2 V to 5.5 V, which allows it to be used in a broad
range of systems. The low propagation delay allows fast switching and higher operation speeds. In addition, the
low-power consumption makes this device a good choice for portable and battery power-sensitive applications.
8.4 Device Functional Modes
Table 1 lists the functional modes for SN74AHC1G08.
Table 1. Function Table
INPUTS
8
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A common application for AND gates is their use in power sequencing. Power sequencing is often employed in
applications that require a processor or other delicate device with specific voltage timing requirements in order to
protect the device from malfunctioning. Using the SN74AHC1G08 to verify that the processor has turned on can
protect it from any harmful signals.
9.2 Typical Application
VCC = 5 V
A
Y
MCU
(MSP43x)
B
Temp.
EN Sensor
VO
Figure 4. Power Sequencing Application
9.2.1 Design Requirements
The SN74AHC1G08 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
The SN74AHC1G08 allows switching control of analog and digital signals with a digital control signal. All
input signals should remain as close to either 0 V or VCC as possible for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
2. Recommended output conditions:
– Load currents should not exceed ±50 mA.
3. Frequency selection criterion:
– The effects of frequency upon the device's power consumption should be studied in CMOS Power
Consumption and CPD Calculation, SCAA035.
– Added trace resistance and capacitance can reduce maximum frequency capability; follow the layout
practices listed in the Layout section.
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Typical Application (continued)
9.2.3 Application Curves
Figure 5. AHC Family VOH vs IOH at VCC = 5.5 V
Figure 6. AHC Family VOL vs IOL at VCC = 5.5 V
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF bypass capacitor is
recommended for devices with a single supply. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. Use multiple bypass capacitors in parallel to reject different frequencies of noise. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close
to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 7 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
10
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11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 7. Trace Example
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• CMOS Power Consumption and CPD Calculation, SCAA035
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AHC1G08DBV3
ACTIVE
SOT-23
DBV
5
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-55 to 125
A08Y
SN74AHC1G08DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
(A083, A08G, A08J,
A08L, A08S)
SN74AHC1G08DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
A08G
SN74AHC1G08DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
A08G
SN74AHC1G08DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
(A083, A08G, A08J,
A08L, A08S)
SN74AHC1G08DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
A08G
SN74AHC1G08DCK3
ACTIVE
SC70
DCK
5
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-55 to 125
AEY
SN74AHC1G08DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
(AE3, AEG, AEJ, AE
L, AES)
SN74AHC1G08DCKRE4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
AE3
SN74AHC1G08DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
AE3
SN74AHC1G08DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
(AE3, AEG, AEJ, AE
L, AES)
SN74AHC1G08DCKTE4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
AE3
SN74AHC1G08DCKTG4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
AE3
SN74AHC1G08DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-55 to 125
(AEB, AES)
SN74AHC1G08DRLRG4
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
Level-1-260C-UNLIM
-55 to 125
(AEB, AES)
(1)
NIPDAUAG
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of