SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709 – FEBRUARY 2008
•
•
•
•
FEATURES
1
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Operating Range of 2 V to 5.5 V
•
•
•
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
1
B
2
GND
3
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
A
Max tpd of 10 ns at 5 V
Low Power Consumption, 10 µA Max ICC
±8 mA Output Drive at 5 V
Schmitt Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
Latch-Up Performance Exceeds 250 mA Per
JESD 17
A
1
B
2
GND
3
5
VCC
5
4
DRL PACKAGE
(TOP VIEW)
VCC
Y
A
1
B
2
GND
3
5
VCC
4
Y
Y
4
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The SN74AHC1G86 is a single 2-input exclusive-OR gate. The device performs the Boolean function Y = A ⊕ B
or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
ORDERING INFORMATION (1)
TA
–55°C to 125°C
(1)
(2)
(3)
PACKAGE (2)
SOT (SC-70) - DCK
Reel of 3000
ORDERABLE PART
NUMBER
SN74AHC1G86MDCKREP
TOP-SIDE MARKING (3)
CGB
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
The actual top-side marking has one additional character that designates the assembly/test site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709 – FEBRUARY 2008
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AHC1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
EVEN-PARITY ELEMENT
=
2k
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
ODD-PARITY ELEMENT
2k + 1
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO = 0 to VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
Continuous current through VCCor GND
VCC or GND
±50
mA
252
°C/W
150
°C
θJA
Package thermal impedance
Tstg
Storage temperature range
(1)
(2)
(3)
2
(3)
DCK package
–65
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC1G86-EP
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709 – FEBRUARY 2008
Recommended Operating Conditions (1)
MIN
VCC
Supply voltage
VIH
High-level input voltage
MAX
2
VCC = 2 V
1.5
VCC = 3 V
2.1
VCC = 5.5 V
UNIT
5.5
V
V
3.85
VCC = 2 V
0.5
VCC = 3 V
0.9
VIL
Low-level input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
µA
VCC = 5.5 V
1.65
VCC = 2 V
IOH
High-Level output current
IOL
Low-Level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
VCC = 3.3 V ± 0.3 V
–4
VCC = 5 V ± 0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ± 0.3 V
4
VCC = 5 V ± 0.5 V
8
VCC = 3.3 V ± 0.3 V
100
VCC = 5 V ± 0.5 V
20
–55
V
mA
µA
mA
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC1G86-EP
3
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709 – FEBRUARY 2008
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –50 µA
TA = –55°C TO 125°C
TYP
2V
1.9
2
1.9
2.9
3V
2.9
3
4.5 V
4.4
4.5
IOH = –4 mA
3V
2.58
IOH = –8 mA
4.5 V
3.94
VOH
IOL = 50 µA
VOL
IOL = 4 mA
IOL = 8 mA
II
TA = 25°C
MIN
VI = 5.5 V or GND
ICC
VI = VCC or GND, O = 0
Ci
VI = VCC or GND
MAX
MIN
MAX
4.4
UNIT
V
2.48
3.8
2V
0.1
0.1
3V
0.1
0.1
4.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
0 V to 5.5 V
±0.1
±1
µA
1
10
µA
10
10
pF
5.5 V
5V
4
V
Switching Characteristics
over operating free-air temperature range, VCC = 3.3 ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 50 pF
TA = 25°C
MIN
tPHL
TA = –55°C TO 125°C
UNIT
TYP
MAX
MIN
MAX
9.5
14.5
1
16.5
ns
9.5
14.5
1
16.5
ns
Switching Characteristics
over operating free-air temperature range, VCC = 5 ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 50 pF
TA = 25°C
MIN
TA = –55°C TO 125°C
TYP
MAX
MIN
MAX
6.3
8.8
1
10
6.3
8.8
1
10
UNIT
ns
Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
TEST CONDITIONS
No load, f = 1 MHz
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TYP
18
UNIT
pF
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC1G86-EP
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709 – FEBRUARY 2008
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
CL
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
50% VCC
Input
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
VCC
Output
Control
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC1G86-EP
5
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AHC1G86MDCKRE
P
Package Package Pins
Type Drawing
SC70
DCK
5
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
2.4
B0
(mm)
K0
(mm)
P1
(mm)
2.5
1.2
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC1G86MDCKREP
SC70
DCK
5
3000
202.0
201.0
28.0
Pack Materials-Page 2
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