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SN74AHC1GU04
SCLS343S – APRIL 1996 – REVISED OCTOBER 2016
SN74AHC1GU04 Single Inverter Gate
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
1
•
Operating Range of 2-V to 5.5-V VCC
Unbuffered Output
±8-mA Output Drive at 5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
Wireless and Telecom Infrastructure
Audio Mixers
TVs
Set-Top-boxes
Audio
Servers
Cameras: Surveillance
Software Defined Radio (SDR)
3 Description
The SN74AHC1GU04 device contains a single
inverter gate. The device performs the Boolean
function Y = A.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AHC1GU04DBV SOT-23 (5)
2.90 mm x 1.60 mm
SN74AHC1GU04DCK SC-70 (5)
2.00 mm x 1.30 mm
SN74AHC1GU04DRL
1.65 mm x 1.20 mm
SOT (5)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
Y
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1GU04
SCLS343S – APRIL 1996 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
5
5
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision R (December 2014) to Revision S
Page
•
Deleted "2-Input" from data sheet title ................................................................................................................................... 1
•
Added missing package names.............................................................................................................................................. 1
•
Changed "SOT-553" to "SOT" ............................................................................................................................................... 1
•
Changed "IOH = 50 µA" to "IOL = 50 µA" for VOL in Electrical Characteristics table ................................................................ 5
•
Changed Typical Application Schematic with a more accurate image................................................................................... 9
•
Added Receiving Notification of Documentation Updates section and Community Resources section .............................. 12
Changes from Revision Q (June 2005) to Revision R
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed MAX operating temperature in Recommended Operating Conditions table. ......................................................... 4
2
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SCLS343S – APRIL 1996 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
NC
1
A
2
GND
3
DRL Package
5-Pin SOT
Top View
5
4
VCC
Y
NC
1
A
2
GND
3
Not to scale
5
VCC
4
Y
Not to scale
DCK Package
5-Pin SC70
Top View
NC
1
A
2
GND
3
5
VCC
4
Y
Not to scale
NC – No internal connection
See mechanical drawings for dimensions.
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
NC
—
2
A
I
No connection
3
GND
—
Ground pin
Input A
4
Y
O
Output Y
5
VCC
—
Power pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
(2)
MIN
MAX
UNIT
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
(2)
Continuous current through each VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
UNIT
2
5.5
V
VCC = 2 V
1.7
VCC = 3 V
2.4
VCC = 5.5 V
4.4
V
VCC = 2 V
0.3
VCC = 3 V
0.6
VIL
Low-level input voltage
VIH
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
VCC = 2 V
–50
µA
VCC = 3.3 V ± 0.3 V
–4
VCC = 5 V ± 0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ± 0.3 V
4
VCC = 5 V ± 0.5 V
8
VCC = 5.5 V
IOH
IOL
TA
(1)
4
High-level output current
Low-level output current
Operating free-air temperature
V
1.1
–40
125
V
mA
µA
mA
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs (SCBA004).
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6.4 Thermal Information
SN74AHC1GU04
THERMAL METRIC
DBV
(SOT-23)
(1)
DCK
(SC70)
DRL
(SOT)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
231.3
287.6
328.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
119.9
97.7
105.1
°C/W
RθJB
Junction-to-board thermal resistance
60.6
65.
150.3
°C/W
ψJT
Junction-to-top characterization parameter
17.8
2.0
6.9
°C/W
ψJB
Junction-to-board characterization parameter
60.1
64.2
148.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –50 µA
VOH
TA = 25°C
2V
1.8
2
1.8
1.9
3V
2.7
3
2.7
2.7
4
4.5
4
4.4
2.48
2.48
IOH = –4 mA
3V
2.58
IOH = –8 mA
4.5 V
3.94
VOL
MAX
MIN
–40°C to +125°C
TYP
4.5 V
IOL = 50 µA
–40°C to +85°C
MIN
MAX
3.8
MIN
MAX
UNIT
V
3.8
2V
0.2
0.2
0.1
3V
0.3
0.3
0.1
4.5 V
0.5
0.5
0.1
IOL = 4 mA
3V
0.36
0.44
0.44
IOL = 8 mA
4.5 V
0.36
0.44
0.44
II
VI = 5.5 V or GND
0 V to
5.5 V
±0.1
±1
±1
µA
ICC
VI = VCC or GND, IO = 0
5.5 V
1
10
10
µA
Ci
VI = VCC or GND
10
10
10
pF
5V
2
V
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
A
Y
CL = 15 pF
A
Y
CL = 50 pF
–40°C to
+85°C
TA = 25°C
MIN
–40°C to +125°C
TYP
MAX
MIN
MAX
MIN
MAX
5
7.1
1
8.5
1
9.5
5
7.1
1
8.5
1
9.5
7.5
10.6
1
12
1
13
7.5
10.6
1
12
1
13
UNIT
ns
ns
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
A
Y
CL = 15 pF
–40°C to
+85°C
TA = 25°C
MIN
–40°C to +125°C
TYP
MAX
MIN
MAX
MIN
MAX
3.5
5.5
1
6
1
6.5
3.5
5.5
1
6
1
6.5
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UNIT
ns
5
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SCLS343S – APRIL 1996 – REVISED OCTOBER 2016
www.ti.com
Switching Characteristics, VCC = 5 V ± 0.5 V (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
A
Y
CL = 50 pF
tPLH
tPHL
–40°C to
+85°C
TA = 25°C
MIN
–40°C to +125°C
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
5
7
1
8
1
8.5
5
7
1
8
1
8.5
ns
6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
TYP
UNIT
7.3
pF
6.9 Typical Characteristics
4.5
7
4
6
3.5
5
TPD (ns)
TPD (ns)
3
2.5
2
4
3
1.5
2
1
1
0.5
TPD in ns
0
-100
TPD in ns
0
-50
0
50
Temperature (qC)
100
150
0
1
D001
Figure 1. TPD vs Temperature
6
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2
3
VCC
4
5
6
D002
Figure 2. TPD vs VCC at 25°C
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SCLS343S – APRIL 1996 – REVISED OCTOBER 2016
7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 3. Load Circuit And Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74AHC1GU04 device contains a single inverter gate. The device performs the Boolean function Y = A.
Internal circuitry consists of a single-stage inverter that can be used in analog applications, such as crystal
oscillators.
8.2 Functional Block Diagram
A
Y
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down-voltage translation
– Inputs accept voltages to 5.5 V
The unbuffered output is ideal for use in oscillator circuits
8.4 Device Functional Modes
Table 1 lists the functional modes of SN74AHC1GU04.
Table 1. Function Table
8
INPUT
A
OUTPUT
Y
H
L
L
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A CMOS inverter is used as a linear amplifier in oscillator applications. Similar to a conventional amplifier, their
open-loop gain is a critical characteristic. The bandwidth of an inverter decreases as the operating voltage
decreases. The open-loop gain of the AHC1GU04 device is shown in Figure 6.
9.2 Typical Application
RF
CMOS Inverter
C1
Crystal
C2
Copyright © 2016, Texas Instruments Incorporated
Figure 5. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads,
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
9.2.3 Application Curve
Figure 6. Open-Loop Gain
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
10
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified inFigure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
74AHC1GU04DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AU4G
74AHC1GU04DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AU4G
74AHC1GU04DCKTG4
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AD3
SN74AHC1GU04DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(AU43, AU4G, AU4J,
AU4L, AU4S)
SN74AHC1GU04DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(AU43, AU4G, AU4J,
AU4L, AU4S)
SN74AHC1GU04DCK3
ACTIVE
SC70
DCK
5
3000
RoHS &
Non-Green
SNBI
Level-1-260C-UNLIM
-40 to 85
ADY
SN74AHC1GU04DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(AD3, ADG, ADJ, AD
L, ADS)
SN74AHC1GU04DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(AD3, ADG, ADJ, AD
L, ADS)
SN74AHC1GU04DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
ADS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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