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SN54AHC245, SN74AHC245
SCLS230J – OCTOBER 1995 – REVISED JULY 2014
SNx4AHC245 Octal Bus Transceivers With 3-State Outputs
1 Features
3 Description
•
•
The SNx4AHC245 octal bus transceivers are
designed for asynchronous two-way communication
between data buses. This part operates from 4.5 V to
5.5 V.
1
•
Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA
Per JESD 17
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
PART NUMBER
SNx4AHC245
2 Applications
•
•
•
•
•
•
Device Information(1)
Servers
PCs and Notebooks
Network Switches
Wearable Health and Fitness Devices
Telecom Infrastructures
Electronic Points of Sale
PACKAGE
BODY SIZE (NOM)
PDIP (20)
25.40 mm x 6.35 mm
SSOP (20)
7.50 mm x 5.30 mm
TSSOP (20)
6.50 mm x 4.40 mm
TVSOP (20)
5.00 mm x 4.40 mm
SOIC (20)
12.80 mm x 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1
DIR
19
OE
A1
2
18
B1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54AHC245, SN74AHC245
SCLS230J – OCTOBER 1995 – REVISED JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
Handling Ratings....................................................... 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Switching Characteristics, VCC = 3.3 V ± 0.3 V ....... 6
Switching Characteristics, VCC = 5 V ± 0.5 V ........... 7
Noise Characteristics ................................................ 7
Operating Characteristics.......................................... 7
Typical Characteristics ............................................ 8
Parameter Measurement Information .................. 9
9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (July 2003) to Revision J
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Added Military Disclaimer to Features list. ............................................................................................................................. 1
•
Added Applications. ............................................................................................................................................................... 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Handling Ratings table. .............................................................................................................................................. 4
•
Changed MAX ambient temperature to 125°C in Recommended Operating Conditions....................................................... 5
•
Added Typical Characteristics. ............................................................................................................................................... 8
•
Added Detailed Description section...................................................................................................................................... 10
•
Added Application and Implementation section.................................................................................................................... 11
•
Added Power Supply Recommendations and Layout sections............................................................................................ 12
2
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SCLS230J – OCTOBER 1995 – REVISED JULY 2014
6 Pin Configuration and Functions
SN54AHC245 . . . J OR W PACKAGE
SN74AHC245 . . . DB, DGV, DW, N, OR PW PACKAGE
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
A3
A4
A5
A6
A7
OE
A2
A1
DIR
VCC
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B1
B2
B3
B4
B5
A8
GND
B8
B7
B6
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN54AHC245 . . . FK PACKAGE
(TOP VIEW)
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
DIR
I/O
Direction Pin
2
A1
I/O
A1 Input/Output
3
A2
I/O
Y4 Input/Output
4
A3
I/O
A2 Input/Output
5
A4
I/O
Y3 Input/Output
6
A5
I/O
A3 Input/Output
7
A6
I/O
Y2 Input/Output
8
A7
I/O
A4 Input/Output
9
A8
I/O
Y1 Input/Output
10
GND
—
Ground Pin
11
B8
I/O
A1 Input/Output
12
B7
I/O
Y4 Input/Output
13
B6
I/O
A2 Input/Output
14
B5
I/O
Y3 Input/Output
15
B4
I/O
A3 Input/Output
16
B
I/O
Y2 Input/Output
17
B2
I/O
A4 Input/Output
18
B2
I/O
Y1 Input/Output
19
B1
I/O
Output Enable
20
VCC
—
Power Pin
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SCLS230J – OCTOBER 1995 – REVISED JULY 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
(2)
VI
Input voltage range
VO
I/O, Output voltage range
Control inputs
IIK
Input clamp current
VI < 0
IOK
I/O, Output clamp current
IO
Continuous output current
MIN
MAX
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
Control inputs
(2)
V
–20
mA
VO < 0 or VO > VCC
±20
mA
VO = 0 to VCC
±25
mA
±75
mA
Continuous current through VCC or GND
(1)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
4
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
1500
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCLS230J – OCTOBER 1995 – REVISED JULY 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHC245
VCC
MIN
MAX
2
5.5
Supply voltage
VIH
High-level input voltage
SN74AHC245
MIN
MAX
2
5.5
VCC = 2 V
1.5
1.5
VCC = 3 V
2.1
2.1
VCC = 5.5 V
3.85
UNIT
V
V
3.85
VCC = 2 V
0.5
0.5
VCC = 3 V
0.9
0.9
VIL
Low-level input voltage
VI
Input voltage
OE or DIR
0
5.5
0
5.5
V
VO
Output voltage
A or B
0
VCC
0
VCC
V
µA
IOH
High-level output current
VCC = 5.5 V
1.65
VCC = 2 V
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
1.65
–50
–50
VCC = 3.3 V ± 0.3 V
–4
–4
VCC = 5 V ± 0.5 V
–8
–8
VCC = 2 V
50
50
VCC = 3.3 V ± 0.3 V
4
4
VCC = 5 V ± 0.5 V
8
8
100
100
20
20
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
–55
V
125
–40
mA
µA
mA
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
DB
THERMAL METRIC (1)
DGV
DW
N
NS
PW
RGY
20 PINS
RθJA
Junction-to-ambient thermal resistance
96.0
116.1
79.8
51.5
77.1
102.8
35.1
RθJC(top)
Junction-to-case (top) thermal resistance
57.7
31.3
45.8
38.2
43.6
36.8
43.3
RθJB
Junction-to-board thermal resistance
51.2
57.6
47.4
32.4
44.6
53.8
12.9
ψJT
Junction-to-top characterization parameter
19.4
1.0
18.5
24.6
17.2
2.5
0.9
ψJB
Junction-to-board characterization
parameter
50.8
56.9
47.0
32.3
44.2
53.3
12.9
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
n/a
n/a
n/a
n/a
n/a
n/a
7.9
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
Copyright © 1995–2014, Texas Instruments Incorporated
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SCLS230J – OCTOBER 1995 – REVISED JULY 2014
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.9
2
1.9
1.9
3V
2.9
3
2.9
2.9
4.5 V
4.4
4.5
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
IOH = –8 mA
4.5 V
3.94
3.8
MIN
MAX
UNIT
V
3.8
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
IOL = 4 mA
3V
0.36
0.5
0.44
IOL = 8 mA
4.5 V
0.36
0.5
0.44
5.5 V
±0.1
±1
±1
0 V to 5.5 V
±0.1
±1 (1)
±1
5.5 V
±0.25
±2.5
±2.5
µA
4
40
40
µA
10
pF
VI = VCC or GND
VI = VCC or GND,
IO = 0
5.5 V
Ci
OE or DIR
VI = VCC or GND
5V
2.5
Cio
A or B inputs
VI = VCC or GND
5V
4
(1)
(2)
MAX
0.1
VO = VCC or GND,
VI (OE) = VIL or VIH
ICC
MIN
2V
VOL
IOZ (2)
MAX
SN74AHC245
2V
IOL = 50 µA
OE or DIR
SN54AHC245
TYP
VOH
II
TA = 25°C
MIN
IOH = –50 µA
A or B inputs
VCC
10
V
µA
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
The parameter IOZ includes the input leakage current.
7.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
B or A
CL = 15 pF
OE
A or B
CL = 15 pF
OE
A or B
CL = 15 pF
A or B
B or A
CL = 50 pF
OE
A or B
CL = 50 pF
OE
A or B
CL = 50 pF
tsk(o)
(1)
(2)
6
TA = 25°C
MIN
SN54AHC245
SN74AHC245
TYP
MAX
MIN
MAX
MIN
MAX
5.8 (1)
8.4 (1)
1 (1)
10 (1)
1
10
(1)
(1)
(1)
(1)
1
10
5.8
8.4
1
10
8.5 (1)
13.2 (1)
1 (1)
15.5 (1)
1
15.5
8.5 (1)
13.2 (1)
1 (1)
15.5 (1)
1
15.5
8.9 (1)
12.5 (1)
1 (1)
15.5 (1)
1
15.5
(1)
(1)
(1)
15.5 (1)
1
15.5
8.9
12.5
1
8.3
11.9
1
13.5
1
13.5
8.3
11.9
1
13.5
1
13.5
11
16.7
1
19
1
19
11
16.7
1
19
1
19
11.5
15.8
1
18
1
18
11.5
15.8
1
18
1
18
CL = 50 pF
1.5 (2)
1.5
UNIT
ns
ns
ns
ns
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
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SCLS230J – OCTOBER 1995 – REVISED JULY 2014
7.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
B or A
CL = 15 pF
OE
A or B
CL = 15 pF
OE
A or B
CL = 15 pF
A or B
B or A
CL = 50 pF
OE
A or B
CL = 50 pF
OE
A or B
CL = 50 pF
tsk(o)
(1)
(2)
TA = 25°C
MIN
SN54AHC245
SN74AHC245
TYP
MAX
MIN
MAX
MIN
MAX
4 (1)
5.5 (1)
1 (1)
6.5 (1)
1
6.5
(1)
(1)
(1)
6.5 (1)
1
6.5
4
5.5
1
5.8 (1)
8.5 (1)
1 (1)
10 (1)
1
10
(1)
(1)
(1)
(1)
1
10
5.8
8.5
1
10
5.6 (1)
7.8 (1)
1 (1)
9.2 (1)
1
9.2
5.6 (1)
7.8 (1)
1 (1)
9.2 (1)
1
9.2
5.5
7.5
1
8.5
1
8.5
5.5
7.5
1
8.5
1
8.5
7.3
10.6
1
12
1
12
7.3
10.6
1
12
1
12
7
9.7
1
11
1
11
7
9.7
1
11
1
11
1 (2)
CL = 50 pF
UNIT
ns
ns
ns
ns
ns
ns
1
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
7.8 Noise Characteristics (1)
VCC = 5 V, CL = 50 pF, TA = 25°C
SN74AHC245
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.9
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.9
V
VOH(V)
Quiet output, minimum dynamic VOH
4.3
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
3.5
V
1.5
V
Characteristics are for surface-mount packages only.
7.9 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load
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f = 1 MHz
TYP
UNIT
14
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pF
7
SN54AHC245, SN74AHC245
SCLS230J – OCTOBER 1995 – REVISED JULY 2014
www.ti.com
7.10 Typical Characteristics
10
14
TPD in ns
12
8
6
TPD (ns)
TPD (ns)
10
4
8
6
4
2
2
TPD in ns
0
-100
0
-50
0
50
Temperature (qC)
100
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0
1
2
D001
Figure 1. TPD vs Temperature at 3.3 V
8
150
3
VCC (V)
4
5
6
D002
Figure 2. TPD vs VCC at 25°C
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SCLS230J – OCTOBER 1995 – REVISED JULY 2014
8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The
control-function implementation minimizes external timing requirements. The SNx4AHC245 devices allow data
transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied
to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability
of the driver.
9.2 Functional Block Diagram
1
DIR
19
OE
A1
2
18
B1
To Seven Other Channels
9.3 Feature Description
•
•
•
VCC is optimized at 5 V
Allows down voltage translation from 5 V to 3.3 V
– Inputs accept voltage levels up to 5.5 V
Slow edge rates minimize output ringing
9.4 Device Functional Modes
Table 1. Function Table
(Each Transceiver)
INPUTS
OE
10
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DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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SCLS230J – OCTOBER 1995 – REVISED JULY 2014
10 Application and Implementation
10.1 Application Information
The SNx4AHC245A is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it ideal for down
translation.
10.2 Typical Application
Regulated 5 V
Regulated 5 V or 3.3 V
OE
VCC
OE
DIR
A1
DIR
B1
µC
5 V LEDs, Relays,
or other system boards
A8
VCC
B8
3.3 V µC
5 V LEDs, Relays,
or other system
or other system boards
A1
B1
µC
A8
B8
boards
GND
GND
5 V LEDs, Relays,
or other system
boards
Figure 4. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive but the high drive will also create faster edges into light loads, so routing and load
conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHC245 SN74AHC245
Submit Documentation Feedback
11
SN54AHC245, SN74AHC245
SCLS230J – OCTOBER 1995 – REVISED JULY 2014
www.ti.com
Typical Application (continued)
10.2.3 Application Curves
AC245
HC245
AHC245
Figure 5. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 6. Layout Diagram
12
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Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHC245 SN74AHC245
SN54AHC245, SN74AHC245
www.ti.com
SCLS230J – OCTOBER 1995 – REVISED JULY 2014
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHC245
Click here
Click here
Click here
Click here
Click here
SN74AHC245
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHC245 SN74AHC245
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9681801Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629681801Q2A
SNJ54AHC
245FK
5962-9681801QRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681801QR
A
SNJ54AHC245J
5962-9681801QSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681801QS
A
SNJ54AHC245W
5962-9681801VSA
ACTIVE
CFP
W
20
25
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681801VS
A
SNV54AHC245W
SN74AHC245DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
SN74AHC245DGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
SN74AHC245DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
SN74AHC245DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
SN74AHC245DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
SN74AHC245DWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
SN74AHC245N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC245N
SN74AHC245NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
SN74AHC245PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
SN74AHC245PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
HA245
SN74AHC245PWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC245PWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
SNJ54AHC245FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629681801Q2A
SNJ54AHC
245FK
SNJ54AHC245J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681801QR
A
SNJ54AHC245J
SNJ54AHC245W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681801QS
A
SNJ54AHC245W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of