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SN54AHC273, SN74AHC273
SCLS376I – JUNE 1997 – REVISED MARCH 2015
SNx4AHC273 Octal D-Type Flip-Flops With Clear
1 Features
3 Description
•
•
•
•
•
These devices are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
1
•
•
Operating Range 2-V to 5.5-V VCC
Contain Eight Flip-Flops With Single-Rail Outputs
Direct Clear Input
Individual Data Input to Each Flip-Flop
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
Information at the data (D) inputs meeting the setup
time requirements is transferred to the Q outputs on
the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the
positive-going pulse. When CLK is at either the high
or low level, the D input has no effect at the output.
Device Information(1)
PART NUMBER
PACKAGE
SNx4AHC273
2 Applications
•
•
•
•
•
•
•
•
BODY SIZE (NOM)
PDIP (20)
24.33 mm × 6.35 mm
SSOP (20)
7.20 mm × 5.30 mm
TSSOP (20)
6.50 mm × 4.40 mm
TVSOP (20)
5.00 mm × 4.40 mm
SOIC (20)
12.80 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Buffers and Storage Registers
Shift Registers
Pattern Generators
Servers
PCs and Notebooks
Network Switches
Memory Systems
Databases
4 Simplified Schematics
CLK
1D
2D
3D
4D
3
4
7
8
5D
6D
13
7D
14
8D
17
18
11
1D
1D
C1
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
1
CLR
D
2
5
6
1Q
2Q
3Q
9
12
4Q
15
5Q
C
C
TG
TG
6Q
16
19
7Q
8Q
Q
C
C
C
C
TG
CLK(I)
TG
C
C
C
C
R
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHC273, SN74AHC273
SCLS376I – JUNE 1997 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
4
4
4
5
5
5
6
6
6
7
7
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements, VCC = 3.3 V ± 0.3 V ..............
Timing Requirements, VCC = 5 V ± 0.5 V .................
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Noise Characteristics ..............................................
Operating Characteristics........................................
Typical Characteristics ............................................
8
9
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ................................................................... 9
Functional Block Diagrams ....................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ................................................ 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
Changes from Revision H (July 2014) to Revision I
•
Page
Changed IOH test conditions for VOH from mA to µA to fix typographical error. ..................................................................... 5
Changes from Revision G (June 1997) to Revision H
Page
•
Updated document to new TI data sheet standards. ............................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Added Military Disclaimer to Features list. ............................................................................................................................. 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating temperature from 85°C to 125°C in Recommended Operating Conditions table. ........................ 4
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added Typical Characteristics. ............................................................................................................................................... 7
•
Added Detailed Description section........................................................................................................................................ 9
•
Added Application and Implementation section.................................................................................................................... 11
2
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Product Folder Links: SN54AHC273 SN74AHC273
SN54AHC273, SN74AHC273
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SCLS376I – JUNE 1997 – REVISED MARCH 2015
6 Pin Configuration and Functions
20
2
19
3
18
4
17
5
16
15
6
7
14
8
13
9
12
10
11
1D
1Q
CLR
VCC
1
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
2D
2Q
3Q
3D
4D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
8Q
SN54AHC273 . . . FK PACKAGE
(TOP VIEW)
SN54AHC273 . . . J OR W PACKAGE
SN74AHC273 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NO.
I/O
NAME
DESCRIPTION
1
CLR
I
Clear Pin
2
1Q
O
1Q Output
3
1D
I
1D Input
4
2D
I
2D Input
5
2Q
O
2Q Output
6
3Q
O
3Q Output
7
3D
I
3D Input
8
4D
I
4D Input
9
4Q
O
4Q Output
10
GND
—
Ground Pin
11
CLK
I
Clock Pin
12
5Q
O
5Q Output
13
5D
I
5D Input
14
6D
I
6D Input
15
6Q
O
6Q Output
16
7Q
O
7Q Output
17
7D
I
7D Input
18
8D
I
8D Input
19
8Q
O
8Q Output
20
VCC
—
Power Pin
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SCLS376I – JUNE 1997 – REVISED MARCH 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±75
mA
Continuous current through VCC or GND
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHC273
VCC
Supply voltage
VIH
High-level input voltage
MAX
MIN
MAX
2
5.5
2
5.5
VCC = 2 V
1.5
VCC = 3 V
2.1
2.1
3.85
3.85
VCC = 5.5 V
VCC = 2 V
VIL
Low-level input voltage
VCC = 3 V
Input voltage
VO
Output voltage
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise and fall time
TA
Operating free-air temperature
(1)
4
V
V
0.5
0.9
0.9
1.65
1.65
0
5.5
0
5.5
0
VCC
0
V
V
VCC
V
–50
–50
µA
VCC = 3 V ± 0.3 V
–4
–4
VCC = 5.5 V ± 0.5 V
–8
–8
VCC = 2 V
VCC = 2 V
IOH
UNIT
1.5
0.5
VCC = 5.5 V
VI
SN74AHC273
MIN
50
50
VCC = 3 V ± 0.3 V
4
4
VCC = 5.5 V ± 0.5 V
8
8
100
100
20
20
VCC = 3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
–55
125
–40
125
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, (SCBA004).
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SCLS376I – JUNE 1997 – REVISED MARCH 2015
7.4 Thermal Information
SN74AHC273
THERMAL METRIC (1)
N
DW
NS
DB
PW
DGV
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
53.9
81.8
79.4
98.7
104.7
118.1
RθJC(top)
Junction-to-case (top) thermal
resistance
38.8
47.8
45.9
60.4
38.8
33.4
RθJB
Junction-to-board thermal resistance
34.7
49.4
46.9
56.9
55.7
59.6
ψJT
Junction-to-top characterization
parameter
26.9
20.1
19.1
21.6
2.9
1.1
ψJB
Junction-to-board characterization
parameter
34.7
49.0
46.5
53.5
55.1
58.9
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
n/a
n/a
n/a
n/a
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the TI application report IC Package Thermal Metrics (SPRA953).
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
TYP
SN54AHC273
MAX
MIN
MAX
SN74AHC273
MIN
2V
1.9
1.9
1.9
2.9
3V
2.9
2.9
4.4
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
IOH = –8 mA
4.5 V
3.94
3.8
MAX
UNIT
V
3.8
2V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
IOL = 4 mA
3V
0.36
0.5
0.44
IOL = 8 mA
4.5 V
0.36
0.5
0.44
0 to 5.5
V
±0.1
±1 (1)
±1
µA
4
40
40
µA
10
pF
IOL = 50 µA
VOL
(1)
MIN
4.5 V
VOH
II
TA = 25°C
VCC
VI = 5.5 V or GND
ICC
VI = VCC or GND IO = 0
Ci
VI = VCC or GND
5.5 V
5V
2.5
10
V
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
7.6 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54AHC273
TA = 25°C
MIN
tw
Pulse Duration
tsu
Setup time
th
Hold time, data after CLK↑
MAX
SN74AHC273
MIN
MAX
TA = 25°C
MIN
MAX
MIN
CLR low
5
6
5
6
CLK high or low
5
6.5
5
6.5
Data before CLK↑
5.5
6.5
5.5
6.5
CLR before CLK↑
2.5
2.5
2.5
2.5
1.5
2
1
1
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MAX
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UNIT
ns
ns
ns
5
SN54AHC273, SN74AHC273
SCLS376I – JUNE 1997 – REVISED MARCH 2015
www.ti.com
7.7 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54AHC273
TA = 25°C
MIN
tw
Pulse Duration
tsu
Setup time
th
Hold time, data after CLK↑
MAX
SN74AHC273
MIN
MAX
TA = 25°C
MIN
MAX
MIN
CLR low
5
5
5
5
CLK high or low
5
5
5
5
Data before CLK↑
4.5
4.5
4.5
4.5
CLR before CLK↑
2
2
2
2
1.5
2
1
1
MAX
UNIT
ns
ns
ns
7.8 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
CLR
Q
(1)
(2)
SN54AHC273
SN74AHC273
MIN
TYP
CL = 15 pF
75 (1)
120 (1)
65 (1)
65
CL = 50 pF
50
75
45
45
CL = 15 pF
CKL
Q
CL = 15 pF
CLR
Q
CL = 50 pF
CLK
Q
CL = 50 pF
tsk(o)
TA = 25°C
LOAD
CAPACITANCE
MAX
MIN
MAX
MIN
MAX
UNIT
MHz
8.9 (1) 13.6 (1)
1 (1)
16 (1)
1
16
8.7 (1) 13.6 (1)
1 (1)
16 (1)
1
16
8.7 (1) 13.6 (1)
1 (1)
16 (1)
ns
1
16
11.4
17.1
1
19.5
1
19.5
11.2
17.1
1
19.5
1
19.5
ns
17.1
1
19.5
1
19.5
ns
1.5
ns
11.2
1.5 (2)
CL = 50 pF
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
7.9 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
CLR
Q
6
TA = 25°C
SN54AHC273
TYP
CL = 15 pF
120 (1)
165 (1)
100 (1)
100
CL = 50 pF
80
110
70
70
CL = 15 pF
Q
CL = 15 pF
CLR
Q
CL = 50 pF
CLK
Q
CL = 50 pF
MAX
MIN
MAX
SN74AHC273
MIN
CKL
tsk(o)
(1)
(2)
LOAD
CAPACITANCE
MIN
MAX
MHz
5.2 (1)
8.5 (1)
1 (1)
10 (1)
1
10
(1)
(1)
(1)
10.5 (1)
1
10.5
5.8
9
1
UNIT
ns
5.8 (1)
9 (1)
1 (1)
10.5 (1)
1
10.5
6.7
10.5
1
12
1
12
7.3
11
1
12.5
1
12.5
ns
7.3
11
1
12.5
1
12.5
ns
1
ns
CL = 50 pF
1 (2)
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
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SCLS376I – JUNE 1997 – REVISED MARCH 2015
7.10 Noise Characteristics (1)
VCC = 5 V, CL = 50 pF, TA = 25°C
SN74AHC273
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.7
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.7
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
3.5
V
1.5
V
TYP
UNIT
Characteristics are for surface-mount packages only.
7.11 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
31
pF
7.12 Typical Characteristics
14
9.4
TPD in ns
9.2
12
9
TPD (ns)
TPD (ns)
10
8
6
8.8
8.6
8.4
4
8.2
2
8
TPD in ns
0
0
1
2
3
VCC (V)
4
5
6
7.8
-100
-50
D001
Figure 1. TPD vs VCC
0
50
Temperature (qC)
100
150
D002
Figure 2. TPD vs Temperature
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8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data
(D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the
clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition
time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the
output.
The inputs are 5 V tolerant and can be driven from 5-V devices. This feature allows the use of these devices as
down translators in a mixed 5-V to 3.3-V system environment.
9.2 Functional Block Diagrams
CLK
1D
2D
3D
4D
3
4
7
8
5D
6D
13
7D
14
8D
17
18
11
1D
1D
C1
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
1
CLR
D
2
5
6
1Q
2Q
3Q
9
12
4Q
15
5Q
C
C
TG
TG
6Q
16
19
7Q
8Q
Q
C
C
C
C
TG
CLK(I)
TG
C
C
C
C
R
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9
SN54AHC273, SN74AHC273
SCLS376I – JUNE 1997 – REVISED MARCH 2015
www.ti.com
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Slow edge rates minimize output ringing
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
10
CLR
CLK
D
OUTPUT
Y
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
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Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN54AHC273 SN74AHC273
SN54AHC273, SN74AHC273
www.ti.com
SCLS376I – JUNE 1997 – REVISED MARCH 2015
10 Application and Implementation
10.1 Application Information
The SNx4AHC273 is a low-drive CMOS device that can be used for a multitude of applications where output
ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs.
The inputs are tolerant to 5.5 V at any valid VCC. This feature makes the device ideal for translating down to the
VCC level. Figure 5 shows the reduction in ringing compared to higher drive parts such as AC.
10.2 Typical Application
Regulated 3.3 V
CLR
VCC
CLK
1Q
1D
5V
System Logic
µC or
8Q
8D
System Logic
GND
Figure 4. Specific Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended input conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 75 mA total for the part
– Outputs should not be pulled above VCC
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN54AHC273 SN74AHC273
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11
SN54AHC273, SN74AHC273
SCLS376I – JUNE 1997 – REVISED MARCH 2015
www.ti.com
Typical Application (continued)
10.2.3 Application Curves
Figure 5. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1
μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 6 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally inputs will be
tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 6. Layout Diagram
12
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Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN54AHC273 SN74AHC273
SN54AHC273, SN74AHC273
www.ti.com
SCLS376I – JUNE 1997 – REVISED MARCH 2015
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHC273
Click here
Click here
Click here
Click here
Click here
SN74AHC273
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN54AHC273 SN74AHC273
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13
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9853001Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629853001Q2A
SNJ54AHC
273FK
5962-9853001QRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9853001QR
A
SNJ54AHC273J
5962-9853001QSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9853001QS
A
SNJ54AHC273W
SN74AHC273DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA273
SN74AHC273DGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA273
SN74AHC273DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC273
SN74AHC273DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC273
SN74AHC273N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC273N
SN74AHC273NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC273
SN74AHC273PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA273
SN74AHC273PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA273
SNJ54AHC273FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629853001Q2A
SNJ54AHC
273FK
SNJ54AHC273J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9853001QR
A
SNJ54AHC273J
SNJ54AHC273W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9853001QS
A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SNJ54AHC273W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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