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SN74AHC595
SCLS373K – MAY 1996 – REVISED SEPTEMBER 2015
SN74AHC595 8-Bit Shift Registers With 3-State Output Registers
1 Features
3 Description
•
•
•
The SN74AHC595 device contains an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel 3state outputs. Separate clocks are provided for both
the shift and storage registers. The shift register has
a direct overriding clear (SRCLR) input, a serial
(SER) input, and a serial output for cascading. When
the output-enable (OE) input is high, all outputs
except QH′ are in the high-impedance state.
1
•
Operating Range: 2-V to 5.5-V VCC
8-Bit Serial-In, Parallel-Out Shift
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Device Information
2 Applications
•
•
•
•
PART NUMBER
Network Switches
Power Infrastructures
LED Displays
Servers
PACKAGE
BODY SIZE (NOM)
SN74AHC595N
PDIP (16)
19.31 mm × 6.35 mm
SN74AHC595D
SOIC (16)
9.90 mm × 3.90 mm
SN74AHC595DB
SSOP (16)
6.20 mm × 5.30 mm
SN74AHC595PW
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D Q
C1
R
3D
C3 Q
15
2D Q
C2
R
3D
C3 Q
1
2D Q
C2
R
3D
C3 Q
2
2D Q
C2
R
3D
C3 Q
3
2D Q
C2
R
3D
C3 Q
4
2D Q
C2
R
3D
C3 Q
5
2D Q
C2
R
3D
C3 Q
6
2D Q
C2
R
3D
C3 Q
7
QA
QB
QC
9
QD
QE
QF
QG
QH
QH′
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC595
SCLS373K – MAY 1996 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Operating Characteristics.......................................... 6
Timing Requirements: VCC = 3.3 V ± 0.3 V .............. 6
Timing Requirements: VCC = 5 V ± 0.5 V ................. 7
Switching Characteristics: VCC = 3.3 V ± 0.3 V ........ 7
Switching Characteristics: VCC = 5 V ± 0.5 V ......... 9
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (July 2013) to Revision K
Page
•
Deleted SN54AHC595 device from the data sheet ............................................................................................................... 1
•
Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Detailed
Description section, Applications and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
Changes from Revision I (June 2004) to Revision J
Page
•
Changed Updated document to new TI data sheet format. ................................................................................................... 1
•
Extended operating temperature range to 125°C................................................................................................................... 4
2
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SCLS373K – MAY 1996 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
D, DB, N, PW Packages
16-Pin SOIC, SSOP, PDIP, TSSOP
Top View
QB
QC
QD
QE
QF
QG
QH
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QA
SER
OE
RCLK
SRCLK
SRCLR
QH′
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
8
—
OE
13
I
Ground Pin
Output Enable
QA
15
O
QA Output
QB
1
O
QB Output
QC
2
O
QC Output
QD
3
O
QD Output
QE
4
O
QE Output
QF
5
O
QF Output
QG
6
O
QG Output
QH
7
O
QH Output
QH'
9
O
QH' Output
RCLK
12
I
RCLK Input
SER
14
I
SER Input
SRCLK
11
I
SRCLK Input
SRCLR
10
I
SRCLR Input
VCC
16
—
Power Pin
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SCLS373K – MAY 1996 – REVISED SEPTEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
(VI < 0)
–20
mA
IOK
Output clamp current
(VO < 0 or VO > VCC)
±20
mA
IO
Continuous output current
(VO = 0 to VCC)
±25
mA
±75
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
Supply voltage
VIH
High-level input voltage
2
VCC = 2 V
1.5
VCC = 3 V
2.1
VCC = 5.5 V
NOM
MAX
5.5
UNIT
V
V
3.85
VCC = 2 V
0.5
VCC = 3 V
0.9
VIL
Low-level Input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
µA
VCC = 5.5 V
1.65
VCC = 2 V
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
VCC = 3.3 V ± 0.3 V
–4
VCC = 5 V ± 0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ± 0.3 V
4
VCC = 5 V ± 0.5 V
8
VCC = 3.3 V ± 0.3 V
100
VCC = 5 V ± 0.5 V
20
–40
125
V
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74AHC595
THERMAL METRIC (1)
D (SOIC)
DB (SSOP)
N (PDIP)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
73
97.8
47.8
106.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
—
48.1
35.1
40.8
°C/W
RθJB
Junction-to-board thermal resistance
—
48.5
27.8
51.1
°C/W
ψJT
Junction-to-top characterization parameter
—
10.0
20.1
3.8
°C/W
ψJB
Junction-to-board characterization parameter
—
47.9
27.7
50.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
VCC
TA = 25°C
IOH = –50 µA
TA = –40°C to 85°C
2V
3V
4.5 V
2.58
TA = –40°C to 85°C
3V
2.48
TA = –40°C to 125°C Recommended
2.48
TA = 25°C
3.94
TA = –40°C to 85°C
4.5 V
3.8
TA = –40°C to 125°C Recommended
3.8
TA = 25°C
0.1
TA = –40°C to 85°C
2V
0.1
TA = –40°C to 125°C Recommended
0.1
TA = 25°C
IOL = 50 µA
0.1
TA = –40°C to 85°C
3V
0.1
TA = –40°C to 125°C Recommended
0.1
TA = 25°C
VOL
IOL = 50 µA
0.1
TA = –40°C to 85°C
4.5 V
0.1
TA = –40°C to 125°C Recommended
0.36
TA = –40°C to 85°C
3V
0.44
TA = –40°C to 125°C Recommended
0.44
TA = 25°C
IOL = 8 mA
0.36
TA = –40°C to 85°C
4.5 V
0.44
TA = –40°C to 125°C Recommended
0.44
TA = 25°C
II
VI = 5.5 V or GND
±0.1
TA = –40°C to 85°C
0 V to 5.5 V
±1
TA = –40°C to 125°C Recommended
IOZ
(1)
QA – QH
TA = –40°C to 85°C
µA
±1
TA = 25°C
VI = VCC or GND,
VO = VCC or GND,
OE = VIH or VIL,
V
0.1
TA = 25°C
IOL = 4 mA
V
4.4
TA = 25°C
IOL = 50 µA
4.5
4.4
TA = –40°C to 125°C Recommended
IOH = –8 mA
3
2.9
4.4
TA = –40°C to 85°C
UNIT
2.9
TA = 25°C
IOH = –4 mA
2
2.9
TA = –40°C to 85°C
TA = –40°C to 125°C Recommended
IOH = –50 µA
1.9
MAX
1.9
TA = 25°C
VOH
TYP
1.9
TA = –40°C to 125°C Recommended
IOH = –50 µA
MIN
±0.25
±2.5
5.5 V
TA = –40°C to 125°C
Recommended
μA
±2.5
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
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SCLS373K – MAY 1996 – REVISED SEPTEMBER 2015
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
TA = 25°C
ICC
VI = VCC or GND,
IO = 0
TA = –40°C to 85°C
40
5.5 V
TA = –40°C to 125°C
Recommended
Ci
VI = VCC or GND
CO
VO = VCC or GND,
UNIT
4
TA = 25°C
3
5V
TA = –40°C TO 85°C
TA = 25°C
µA
40
10
pF
10
5V
5.5
pF
6.6 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
TYP
UNIT
25.2
pF
6.7 Timing Requirements: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
MIN
SRCLK high or low
tW
Pulse duration
RCLK high or low
SRCLR low
TA = 25°C
5
TA = –40°C to 85°C
5
TA = –40°C to 125°C Recommended
6
TA = 25°C
5
TA = –40°C to 85°C
5
TA = –40°C to 125°C Recommended
6
TA = 25°C
5
TA = –40°C to 85°C
SER before SRCLK↑
tsu
Set-up time
6.5
TA = 25°C
3.5
TA = –40°C to 85°C
3.5
TA = –40°C to 125°C Recommended
4.5
8.5
TA = –40°C to 125°C Recommended
9.5
8
TA = –40°C to 85°C
(1)
6
Hold time
SER after SRCLK↑
10
TA = 25°C
3
TA = –40°C to 85°C
3
TA = –40°C to 125°C Recommended
th
ns
9
TA = –40°C to 125°C Recommended
SRCLR high (inactive) before
SRCLK↑
ns
8
TA = –40°C to 85°C
TA = 25°C
SRCLR low before RCLK↑
UNIT
5
TA = –40°C to 125°C Recommended
TA = 25°C
SRCLK↑ before RCLK↑ (1)
MAX
4
TA = 25°C
1.5
TA = –40°C to 85°C
1.5
TA = –40°C to 125°C Recommended
2.5
ns
This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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6.8 Timing Requirements: VCC = 5 V ± 0.5 V
MIN
SRCLK high or low
tW
Pulse duration
RCLK high or low
SRCLR low
TA = 25°C
5
TA = –40°C to 85°C
5
TA = –40°C to 125°C Recommended
6
TA = 25°C
5
TA = –40°C to 85°C
5
TA = –40°C to 125°C Recommended
6
TA = 25°C
5
TA = –40°C to 85°C
SRCLK↑ before RCLK↑ (1)
tsu
Set-up time
SRCLR low before RCLK↑
th
Hold time
(1)
SER after SRCLK↑
UNIT
ns
6.2
TA = 25°C
3
TA = –40°C to 85°C
3
TA = –40°C to 125°C Recommended
4
TA = 25°C
5
TA = –40°C to 85°C
5
TA = –40°C to 125°C Recommended
6
TA = 25°C
5
TA = –40°C to 85°C
5
TA = –40°C to 125°C Recommended
SRCLR high (inactive) before SRCLK↑
MAX
5
TA = –40°C to 125°C Recommended
SER before SRCLK↑
NOM
ns
6
TA = 25°C
2.5
TA = –40°C to 85°C
2.5
TA = –40°C to 125°C Recommended
3.5
TA = 25°C
2
TA = –40°C to 85°C
2
TA = –40°C to 125°C Recommended
3
ns
This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
6.9 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TEST CONDITIONS
TA = 25°C
CL = 15 pF
fmax
CL = 50 pF
MIN
TYP
80 (1)
120 (1)
TA = –40°C to 85°C
70
TA = –40°C to 125°C Recommended
60
TA = 25°C
55
TA = –40°C to 85°C
50
TA = –40°C to 125°C Recommended
40
tPLH
RCLK
QA – QH
CL = 15 pF
tPHL
RCLK
QA – QH
CL = 15 pF
1
13.5
TA = –40°C to 125°C Recommended
1
14.9
6 (1)
1
13.5
TA = –40°C to 125°C Recommended
1
14.9
6.6 (1)
SRCLK
QH'
CL = 15 pF
1
15
TA = –40°C to 125°C Recommended
1
16.4
6.6 (1)
tPHL
(1)
SRCLK
QH'
CL = 15 pF
ns
13 (1)
TA = –40°C to 85°C
TA = 25°C
ns
11.9 (1)
TA = –40°C to 85°C
TA = 25°C
tPLH
11.9 (1)
TA = –40°C to 85°C
TA = 25°C
UNIT
MHz
105
6 (1)
TA = 25°C
MAX
ns
13 (1)
TA = –40°C to 85°C
1
15
TA = –40°C to 125°C Recommended
1
16.4
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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Switching Characteristics: VCC = 3.3 V ± 0.3 V (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TEST CONDITIONS
MIN
TA = 25°C
tPHL
SRCLR
QH'
CL = 15 pF
OE
QA – QH
CL = 15 pF
OE
QA – QH
CL = 15 pF
6.2
RCLK
QA – QH
CL = 50 pF
13.7
1
15
6 (1)
1
13.5
TA = –40°C to 125°C Recommended
1
14.9
7.8 (1)
TA = –40°C to 85°C
1
TA = –40°C to 125°C Recommended
1
RCLK
QA – QH
CL = 50 pF
SRCLK
QH'
CL = 50 pF
SRCLK
QH'
CL = 50 pF
SRCLR
QH'
CL = 50 pF
17
TA = –40°C to 125°C Recommended
1
18.6
7.9
1
17
TA = –40°C to 125°C Recommended
1
18.6
9.2
1
18.5
TA = –40°C to 125°C Recommended
1
20
OE
QA – QH
CL = 50 pF
1
18.5
TA = –40°C to 125°C Recommended
1
20
1
17.2
TA = –40°C to 125°C Recommended
1
18.7
1
17
TA = –40°C to 125°C Recommended
1
18.6
tPZL
OE
QA – QH
CL = 50 pF
9.6
OE
QA – QH
CL = 50 pF
1
17
TA = –40°C to 125°C Recommended
1
18.6
8.1
8
OE
QA – QH
CL = 50 pF
1
16.2
TA = –40°C to 125°C Recommended
1
17.4
9.3
ns
15.7
TA = –40°C to 85°C
1
16.2
TA = –40°C to 125°C Recommended
1
17.4
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ns
15.7
TA = –40°C to 85°C
TA = 25°C
tPLZ
ns
15
TA = –40°C to 85°C
TA = 25°C
tPHZ
ns
15
TA = –40°C to 85°C
TA = 25°C
ns
16.3
TA = –40°C to 85°C
7.8
ns
16.5
TA = –40°C to 85°C
9
ns
16.5
TA = –40°C to 85°C
9.2
ns
15.4
TA = –40°C to 85°C
TA = 25°C
tPZH
ns
15.4
1
TA = 25°C
tPHL
ns
14.9
TA = –40°C to 85°C
TA = 25°C
tPHL
ns
11.5 (1)
13.5
7.9
TA = 25°C
tPLH
UNIT
11.5 (1)
TA = –40°C to 85°C
TA = 25°C
tPHL
12.8
TA = –40°C to 125°C Recommended
TA = 25°C
tPLH
(1)
1
TA = 25°C
tPZL
MAX
(1)
TA = –40°C to 85°C
TA = 25°C
tPZH
TYP
ns
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6.10 Switching Characteristics: VCC = 5 V ± 0.5 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
CL = 15 pF
fmax
CL = 50 pF
tPLH
RCLK
QA – QH
CL = 15 pF
tPHL
RCLK
QA – QH
CL = 15 pF
tPLH
SRCLK
QH'
CL = 15 pF
tPHL
SRCLK
QH'
CL = 15 pF
tPHL
SRCLR
QH'
CL = 15 pF
tPZH
OE
QA – QH
CL = 15 pF
tPZL
OE
QA – QH
CL = 15 pF
tPLH
RCLK
QA – QH
CL = 50 pF
tPHL
RCLK
QA – QH
CL = 50 pF
tPLH
SRCLK
QH'
CL = 50 pF
tPHL
SRCLK
QH'
CL = 50 pF
tPHL
SRCLR
QH'
CL = 50 pF
tPZH
OE
QA – QH
CL = 50 pF
tPZL
OE
QA – QH
CL = 50 pF
tPHZ
OE
QA – QH
CL = 50 pF
tPLZ
OE
QA – QH
CL = 50 pF
(1)
TEST CONDITIONS
TA = 25°C
TA = –40°C to 85°C
MIN
TYP
(1)
(1)
135
115
TA = 25°C
95
TA = –40°C to 85°C
85
1
TA = –40°C to 85°C
1
TA = –40°C to 85°C
1
TA = –40°C to 85°C
1
TA = –40°C to 85°C
1
TA = –40°C to 85°C
1
TA = –40°C to 85°C
1
TA = 25°C
TA = –40°C to 85°C
TA = –40°C to 85°C
5.6
TA = –40°C to 85°C
5.6
TA = –40°C to 85°C
6.4
TA = –40°C to 85°C
6.4
TA = –40°C to 85°C
6.4
TA = –40°C to 85°C
5.7
TA = –40°C to 85°C
6.8
TA = –40°C to 85°C
3.5
10.3
11
3.4
1
10.6
12
1
TA = 25°C
10.6
12
1
TA = 25°C
10
11.1
1
TA = 25°C
10.2
11.4
1
TA = 25°C
10.2
11.4
1
TA = 25°C
9.4
10.5
1
TA = 25°C
9.4
10.5
1
TA = 25°C
8.6 (1)
10
1
TA = 25°C
8.6 (1)
10
5.4 (1)
TA = 25°C
8 (1)
9.1
4.3 (1)
TA = 25°C
8.2 (1)
9.4
4.5 (1)
TA = 25°C
8.2 (1)
9.4
4.5 (1)
TA = 25°C
7.4 (1)
8.5
4.5 (1)
TA = 25°C
7.4 (1)
8.5
4.3 (1)
TA = 25°C
UNIT
MHz
140
4.3 (1)
TA = 25°C
TA = –40°C to 85°C
170
MAX
10.3
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH′
NOTE:
implies that the output is in 3-State mode.
Figure 1. Timing Diagram
10
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6.11 Typical Characteristics
20
16
12
tpd(ns)
8
4
0
-100
VCC = 3.3 V
-50
0
50
Temperature (°C)
100
150
15-pF Load
Figure 2. SN74AHC595 RCLK to Q TPD vs Temperature
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7 Parameter Measurement Information
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
VCC
Open
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
VCC
50% VCC
50% VCC
0V
th
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
50% VCC
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
VCC
Output
Control
50% VCC
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
12
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8 Detailed Description
8.1 Overview
The SN74AHC595 device is part of the AHC family of logic devices intended for CMOS applications. The
SN74HC595 device is an 8-bit shift register that feeds an 8-bit D-type storage register.
Both the shift-register clock (SRCLK) and storage-register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register is always one clock pulse ahead of the storage register.
8.2 Functional Block Diagram
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D Q
C1
R
3D
C3 Q
15
2D Q
C2
R
3D
C3 Q
1
2D Q
C2
R
3D
C3 Q
2
2D Q
C2
R
3D
C3 Q
3
2D Q
C2
R
3D
C3 Q
4
2D Q
C2
R
3D
C3 Q
5
2D Q
C2
R
3D
C3 Q
6
2D Q
C2
R
3D
C3 Q
7
QA
QB
QC
9
QD
QE
QF
QG
QH
QH′
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8.3 Feature Description
The SN74AHC595 device is an 8-bit serial-in, parallel-out shift registers that have a wide operating voltage range
from 2 V to 5.5 V and a low current consumption of 40-µA (max) ICC.
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
14
FUNCTION
SER
SRCLK
SRCLR
RCLK
OE
X
X
X
X
H
Outputs QA−QH are disabled.
X
X
X
X
L
Outputs QA−QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X
X
X
↑
X
Shift-register data is stored into the storage register.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AHC595 device is a low-drive CMOS device that can be used for a multitude of bus-interface type
applications where output ringing is a concern. The low drive and slow edge rates minimize overshoot and
undershoot on the outputs. Figure 4 shows an application where eight LEDs are used to visualize the data bits
contained within the shift register.
9.2 Typical Application
SRCLR
SRCLK
5
RCLK
Controller
OE
SER
10
15
11
1
12
2
13
3
14
4
5
6
7
+5V
9
VCC
16
8
QA
1k
QB
1k
QC
QD
QE
QF
QG
QH
1k
1k
1k
1k
1k
1k
Q+¶
GND
0.1 F
Figure 4. Shift Register Display of 8 bits
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care must be taken to avoid bus contention
because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into
light loads, so routing and load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 6.0 V at any valid VCC
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Typical Application (continued)
•
Recommend output conditions:
– Load currents must not exceed 25 mA per output and 75 mA total for the part
– Outputs must not be pulled above VCC
9.2.3 Application Curve
10
8
6
tpd(ns)
4
2
0
-100
VCC = 5 V
-50
0
50
Temperature (°C)
100
150
15-pF Load
Figure 5. SN74AHC595 RCLK to Q TPD vs Temperature
16
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10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply-voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1-μf capacitor is recommended; if there are multiple VCC pins, then a 0.01-μf or a 0.022-μf capacitor is
recommended for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. A 0.1-μf and a 1-μf capacitor are commonly used in parallel. The bypass capacitor must be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be
left unconnected because the undefined voltages at the outside connections results in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally, these unused inputs will
be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs, unless the part is a transceiver. If the transceiver has an output-enable pin, it will disable the output
section of the part when asserted. This will not disable the input section of the I/Os, so they cannot float when
disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, wee the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC595D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC595
SN74AHC595DBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA595
SN74AHC595DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC595
SN74AHC595DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC595
SN74AHC595DRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC595
SN74AHC595DRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC595
SN74AHC595N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC595N
SN74AHC595PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA595
SN74AHC595PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA595
SN74AHC595PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
HA595
SN74AHC595PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA595
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2015
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHC595 :
• Automotive: SN74AHC595-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AHC595DBR
SSOP
DB
16
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74AHC595DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74AHC595DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74AHC595PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHC595PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHC595PWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC595DBR
SSOP
DB
16
2000
367.0
367.0
38.0
SN74AHC595DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74AHC595DR
SOIC
D
16
2500
367.0
367.0
38.0
SN74AHC595PWR
TSSOP
PW
16
2000
364.0
364.0
27.0
SN74AHC595PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74AHC595PWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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