SN54AHC86
SN74AHC86
www.ti.com
SCLS249J – OCTOBER 1995 – REVISED JUNE 2013
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
Check for Samples: SN54AHC86, SN74AHC86
FEATURES
1
Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
1B
1Y
2A
2B
2Y
14
1B
1A
NC
VCC
4B
1
13 4B
2
3
12 4A
4
4Y
10 3B
9 3A
11
5
6
7
8
SN54AHC86 . . . FK PACKAGE
(TOP VIEW)
1Y
NC
2A
NC
2B
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
14
VCC
1
SN74AHC86 . . . RGY PACKAGE
(TOP VIEW)
3Y
1A
1B
1Y
2A
2B
2Y
GND
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1A
SN54AHC86 . . . J OR W PACKAGE
SN74AHC86 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
•
GND
•
•
NC − No internal connection
DESCRIPTION
The ’AHC86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function Y =
A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
FUNCTION TABLE
(EACH GATE)
INPUTS
A
OUTPUT
B
Y
L
L
L
L
H
H
H
L
H
H
H
L
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2013, Texas Instruments Incorporated
SN54AHC86
SN74AHC86
SCLS249J – OCTOBER 1995 – REVISED JUNE 2013
www.ti.com
EXCLUSIVE–OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternativelogic
symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AHC86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
EVEN-PARITY ELEMENT
=
ODD-PARITY ELEMENT
2k
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
2k + 1
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
Supply voltage range, VCC
–0.5 to 7
V
Input voltage range, VI (2)
–0.5 to 7
V
Output voltage range, VO
(2)
–0.5 to VCC + 0.5
V
Input clamp current, IIK (VI < 0)
–20
mA
Output clamp current, IOK (VO < 0 or VO > VCC)
±20
mA
Continuous output current, IO (VO = 0 to VCC)
±25
mA
Continuous current through VCC or GND
±50
mA
D package (3)
86
DB package (3)
DGV package
Package thermal impedance, θJA
96
(3)
127
N package (3)
80
NS package (3)
76
PW package (3)
113
RGY package (4)
47
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
2
°C/W
–65 to 150
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC86 SN74AHC86
SN54AHC86
SN74AHC86
www.ti.com
SCLS249J – OCTOBER 1995 – REVISED JUNE 2013
RECOMMENDED OPERATING CONDITIONS (1)
SN54AHC86
VCC
Supply voltage
VCC= 2 V
VIH
High-level input voltage
VCC= 3V
VCC= 5.5 V
MAX
2
5.5
1.5
Low-level Input voltage
Input voltage
VO
Output voltage
IOL
Low-level output current
Δt/Δv
Input Transition rise or fall rate
TA
Operating free-air temperature
(1)
5.5
2.1
0.5
VCC= 3 V
High-level output current
2
UNIT
V
1.5
3.85
V
0.5
0.9
0.9
1.65
1.65
V
0
5.5
0
5.5
V
0
VCC
0
VCC
V
VCC= 2 V
IOH
MAX
2.1
VCC= 5.5 V
VI
MIN
3.85
VCC= 2 V
VIL
SN74AHC86
MIN
–50
–50
VCC= 3.3 V ± 0.3 V
–4
–4
VCC= 5 V ± 0.5 V
–8
–8
VCC= 2 V
50
50
VCC= 3.3 V ± 0.3 V
4
4
VCC= 5 V ± 0.5 V
8
8
100
100
20
20
VCC= 3.3 V ± 0.3 V
VCC= 5 V ± 0.5 V
–55
125
–40
125
mA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC86 SN74AHC86
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3
SN54AHC86
SN74AHC86
SCLS249J – OCTOBER 1995 – REVISED JUNE 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
SN54AHC86
SN74AHC86
MAX
MIN
MAX
MIN
TA = –40°C TO
125°C
Recommended
MIN
TYP
2V
1.9
2
1.9
1.9
1.9
MAX
MIN
2.9
2.9
3
2.9
2.9
4.4
4.5
4.4
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
2.48
IOH = –8 mA
4.5 V
3.94
VOL
ICC
VI = VCC or
GND,
Ci
VI = VCC or GND
IO = 0
V
3.8
0.1
0.1
0.1
0.1
3V
0.1
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
0.1
3V
0.36
0.5
0.44
0.5
4.5 V
0.36
0.5
0.44
0.5
±0.1
(1)
±1
±1
µA
20
20
20
µA
0 V to 5.5
V
VI = 5.5 V or GND
3.8
MAX
2V
IOH = 4 mA
IOH = 8 mA
3.8
UNIT
SN74AHC86
3V
IOL = 50 µA
(1)
TA = –40°C TO
85°C
4.5 V
VOH
II
TA = 25°C
VCC
TA = –55°C TO
125°C
5.5 V
±1
2
5V
4
10
10
V
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
(1)
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
TA = –40°C TO
125°C
TA = –55°C TO
125°C
TA = –40°C TO
85°C
SN54AHC86
SN74AHC86
SN74AHC86
MIN
MIN
MIN
MAX
MAX
Recommended
TYP
MAX
7 (1)
11 (1)
1 (1)
13 (1)
1
13
1
13
7 (1)
11 (1)
1 (1)
13 (1)
1
13
1
13
9.5
14.5
1
16.5
1
16.5
1
16.5
9.5
14.5
1
16.5
1
16.5
1
16.5
UNIT
MAX
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
(1)
4
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
TA = –55°C TO
125°C
TA = –40°C TO
85°C
SN54AHC86
SN74AHC86
MIN
MIN
MAX
TA = –40°C TO
125°C
Recommended
UNIT
SN74AHC86
TYP
MAX
4.8 (1)
6.8 (1)
1 (1)
8 (1)
1
MAX
8
MIN
1
MAX
8
4.8 (1)
6.8 (1)
1 (1)
8 (1)
1
8
1
8
6.3
8.8
1
10
1
10
1
10
6.3
8.8
1
10
1
10
1
10
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC86 SN74AHC86
SN54AHC86
SN74AHC86
www.ti.com
SCLS249J – OCTOBER 1995 – REVISED JUNE 2013
NOISE CHARACTERISTICS
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHC86
PARAMETER
MIN
TYP
UNIT
MAX
VOL(P)
Quiet output, maximum dynamic VOL
0.3
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.3
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.4
VIH(D)
High-level dynamic input voltage
3.5
VIL(D)
Low-level dynamic input voltage
(1)
V
V
1.5
V
Characteristics are for surface-mount packages only.
OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load,
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC86 SN74AHC86
f = 1 MHz
TYP
18
UNIT
pF
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5
SN54AHC86
SN74AHC86
SCLS249J – OCTOBER 1995 – REVISED JUNE 2013
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
50% VCC
50% VCC
Input
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
tPHL
VOH
In-Phase
Output
50% VCC
50% VCC
VOL
tPHL
Out-of-Phase
Output
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC86 SN74AHC86
SN54AHC86
SN74AHC86
www.ti.com
SCLS249J – OCTOBER 1995 – REVISED JUNE 2013
REVISION HISTORY
Changes from Revision I (July 2003) to Revision J
Page
•
Changed document format from Quicksilver to DocZone. .................................................................................................... 1
•
Extended operating temperature range to 125°C ................................................................................................................. 3
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC86 SN74AHC86
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7
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9681601Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629681601Q2A
SNJ54AHC
86FK
5962-9681601QCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681601QC
A
SNJ54AHC86J
5962-9681601QDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681601QD
A
SNJ54AHC86W
SN74AHC86D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86DBLE
OBSOLETE
SSOP
DB
14
TBD
Call TI
Call TI
-40 to 125
SN74AHC86DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86DGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC86N
SN74AHC86NE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC86N
SN74AHC86NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86PWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 125
SN74AHC86PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Addendum-Page 1
HA86
Samples
PACKAGE OPTION ADDENDUM
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Orderable Device
10-Jun-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC86PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86RGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA86
SN74AHC86RGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA86
SNJ54AHC86FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629681601Q2A
SNJ54AHC
86FK
SNJ54AHC86J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681601QC
A
SNJ54AHC86J
SNJ54AHC86W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9681601QD
A
SNJ54AHC86W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHC86, SN74AHC86 :
• Catalog: SN74AHC86
• Military: SN54AHC86
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AHC86DBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74AHC86DGVR
TVSOP
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74AHC86DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHC86NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74AHC86PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHC86RGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC86DBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74AHC86DGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74AHC86DR
SOIC
D
14
2500
367.0
367.0
38.0
SN74AHC86NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74AHC86PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74AHC86RGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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