参考文献
SN74AHC86, SN54AHC86
ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
SNx4AHC86 四路双输入异或门
1 特性
•
•
•
3 描述
工作电压为 2V 至 5.5V VCC
闩锁性能超过 250mA，
符合 JESD 17 规范
ESD 保护性能超过 JESD 22 规范要求
– 2000V 人体放电模型 (A114-A)
– 200V 机器放电模型 (A115-A)
– 1000V 充电器件模型 (C101)
SNx4AHC86 器件是四路双输入异或门。此类器件以正
逻辑执行布尔函数 Y = A ⊕ B 或 Y = AB + A B。
常用作真/补元件。如果一个输入为低电平，则可在输
出时重新生成真实形态的其他输入。如果一个输入为高
电平，另一个输入的信号则可在输出时重新生成反向信
号。
器件信息
2 应用
•
•
器件型号
额定值
封装(1)
检测输入信号中的相位差
创建可选的逆变器或缓冲器
BQA（WQFN，14）
D（SOIC，14）
DB（SSOP，14）
SN74AHC86
DGV（TVSOP，14）
商用级
N（PDIP，14）
NS（SOP，14）
PW（TSSOP，14）
RGY（VQFN，14）
J（CDIP，14）
SN54AHC86
军用
W（CFP，14）
FK（LCCC，20）
(1)
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AHC86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
EVEN-PARITY ELEMENT
2k
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
ODD-PARITY ELEMENT
2k + 1
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
异或逻辑
本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认
准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。
English Data Sheet: SCLS249
SN74AHC86, SN54AHC86
www.ti.com.cn
ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 描述................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Recommended Operating Conditions.........................4
6.3 Thermal Information....................................................5
6.4 Electrical Characteristics.............................................5
6.5 Switching Characteristics............................................5
6.6 Switching Characteristics............................................6
6.7 Noise Characteristics.................................................. 6
6.8 Operating Characteristics........................................... 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Functional Block Diagram........................................... 8
8.2 Device Functional Modes............................................8
9 Application and Implementation.................................... 9
9.1 Application Information............................................... 9
9.2 Typical Application...................................................... 9
9.3 Power Supply Recommendations............................. 11
9.4 Layout....................................................................... 11
10 Device and Documentation Support..........................13
10.1 Documentation Support (Analog)............................13
10.2 接收文档更新通知................................................... 13
10.3 支持资源..................................................................13
10.4 Trademarks............................................................. 13
10.5 静电放电警告.......................................................... 13
10.6 术语表..................................................................... 13
11 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision K (July 2023) to Revision L (October 2023)
Page
• Updated RθJA values: D = 86 to 124.5, PW = 113 to 147.7, all values in °C/W................................................ 5
• Added Application and Implementation section..................................................................................................9
Changes from Revision J (May 2013) to Revision K (July 2023)
Page
• 更改了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 添加了 器件信息 表..............................................................................................................................................1
• Added the Device and Documentation Support sections................................................................................. 13
• Added the Mechanical, Packaging, and Orderable Information sections......................................................... 13
2
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Product Folder Links: SN74AHC86 SN54AHC86
English Data Sheet: SCLS249
SN74AHC86, SN54AHC86
www.ti.com.cn
ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
1B
1Y
2A
2B
2Y
13 4B
3
12 4A
14
2
1Y
3
2A
4
2B
5
2Y
6
13
PAD
7
8
GND
3Y
4Y
4
11
5
10 3B
9 3A
6
7
8
NC − No internal connection
图 5-2. SN74AHC86 RGY Package, VQFN 14-Pin
(Top View)
1B
1A
NC
VCC
4B
VCC
1
14
4
3 2 1 20 19
18
5
17
6
16
4B
12
4A
11
4Y
10
3B
9
3A
1Y
NC
2A
NC
2B
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1B
1A
1
2
NC − No internal connection
图 5-1. SN54AHC86 J or W Package,
SN74AHC86 D, DB, DGV, N, NS, or PW Package,
14-Pin (Top View)
VCC
14
2
3Y
1
GND
1A
1B
1Y
2A
2B
2Y
GND
1A
5 Pin Configuration and Functions
NC − No internal connection
图 5-3. SN74AHC86 BQA Package, WQFN 14-Pin
(Top View)
图 5-4. SN54AHC86 FK Package, LCCC 20-Pin (Top
View)
表 5-1. Pin Functions
PIN
D, DB, DGV, N, NS, PW,
RGY, J, W, or BQA
FK
1A
1
2
1B
2
1Y
3
2A
2B
2Y
GND
NAME
TYPE(1)
DESCRIPTION
I
Channel 1, Input A
3
I
Channel 1, Input B
4
O
Channel 1, Output Y
4
6
I
Channel 2, Input A
5
8
I
Channel 2, Input B
6
9
O
Channel 2, Output Y
7
10
G
Ground
3Y
8
12
O
Channel 3, Output Y
3A
9
13
I
Channel 3, Input A
3B
10
14
I
Channel 3, Input B
4Y
11
16
O
Channel 4, Output Y
4A
12
18
I
Channel 4, Input A
4B
13
19
I
Channel 4, Input B
VCC
14
20
P
Positive Supply
NC
—
1, 5, 7, 11, 15, 17
—
Not internally connected
—
The thermal pad can be connected to GND or left
floating. Do not connect to any other signal or supply.
Thermal pad(2)
(1)
(2)
Signal Types: I = Input, O = Output, I/O = Input or Output, G = ground, P = power.
BQA package only
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage range, VCC
Input voltage range, VI
(2)
VALUE
UNIT
–0.5 to 7
V
–0.5 to 7
V
–0.5 to VCC + 0.5
V
Input clamp current, IIK (VI < 0)
–20
mA
Output clamp current, IOK (VO < 0 or VO > VCC)
±20
mA
Continuous output current, IO (VO = 0 to VCC)
±25
mA
Continuous current through VCC or GND
±50
mA
–65 to 150
°C
Output voltage range, VO (2)
Storage temperature range, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 Recommended Operating Conditions
SN54AHC86
VCC
Supply voltage
VIH
High-level input voltage
MIN
MAX
MIN
MAX
2
5.5
2
5.5
VCC= 2 V
1.5
1.5
VCC= 3V
2.1
2.1
VCC= 5.5 V
3.85
VCC= 2 V
VIL
Low-level Input voltage
VCC= 3 V
UNIT
V
V
3.85
0.5
VCC= 5.5 V
0.5
0.9
0.9
1.65
1.65
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
VCC= 2 V
IOL
Low-level output current
–50
–50
VCC= 3.3 V ± 0.3 V
–4
–4
VCC= 5 V ± 0.5 V
–8
–8
VCC= 2 V
50
50
4
4
VCC= 3.3 V ± 0.3 V
VCC= 5 V ± 0.5 V
4
SN74AHC86
Δt/Δv
Input Transition rise or fall rate
TA
Operating free-air temperature
VCC= 3.3 V ± 0.3 V
VCC= 5 V ± 0.5 V
–55
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8
8
100
100
20
20
125
–40
125
mA
mA
ns/V
°C
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Product Folder Links: SN74AHC86 SN54AHC86
English Data Sheet: SCLS249
SN74AHC86, SN54AHC86
www.ti.com.cn
ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
6.3 Thermal Information
THERMAL METRIC(1)
R θJA
(1)
(2)
(3)
Junction-toambient
thermal
resistance
D(2)
DB(2)
DGV(2)
N(2)
NS(2)
PW(2)
RGY(3)
BQA
SOIC
SSOP
TVSOP
PDIP
SOP
TSSOP
VQFN
WQFN
14
14
14
14
14
14
14
14
124.5
96
127
80
76
147.7
47
88.3
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5
6.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
SN54AHC86
SN74AHC86
MAX
MIN
MAX
MIN
TA = –40°C TO
125°C
Recommended
MIN
TYP
2V
1.9
2
1.9
1.9
MAX
MIN
1.9
2.9
3
2.9
2.9
2.9
4.4
4.5
4.4
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
2.48
IOH = –8 mA
4.5 V
3.94
3.8
3.8
VOL
ICC
VI = VCC or
GND,
Ci
VI = VCC or GND
IO = 0
V
3.8
0.1
0.1
0.1
0.1
3V
0.1
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
0.1
3V
0.36
0.5
0.44
0.5
4.5 V
0.36
0.5
0.44
0.5
±0.1
±1(1)
±1
±1
µA
2
20
20
20
µA
0 V to 5.5
V
VI = 5.5 V or GND
MAX
2V
IOH = 4 mA
IOH = 8 mA
UNIT
SN74AHC86
3V
IOL = 50 µA
(1)
TA = –40°C TO
85°C
4.5 V
VOH
II
TA = 25°C
VCC
TA = –55°C TO
125°C
5.5 V
5V
4
10
V
10
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
6.5 Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see 图 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
(1)
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
TA = –40°C TO
125°C
TA = –55°C TO
125°C
TA = –40°C TO
85°C
SN54AHC86
SN74AHC86
SN74AHC86
MIN
MIN
MIN
MAX
MAX
Recommended
TYP
MAX
7(1)
11(1)
1(1)
13(1)
1
13
1
13
7(1)
11(1)
1(1)
13(1)
1
13
1
13
9.5
14.5
1
16.5
1
16.5
1
16.5
9.5
14.5
1
16.5
1
16.5
1
16.5
UNIT
MAX
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see 图 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
TA = –55°C TO
125°C
TA = –40°C TO
85°C
SN54AHC86
SN74AHC86
MIN
MIN
MAX
TA = –40°C TO
125°C
Recommended
UNIT
SN74AHC86
TYP
MAX
4.8(1)
6.8(1)
1(1)
8(1)
1
MAX
8
MIN
1
MAX
8
4.8(1)
6.8(1)
1(1)
8(1)
1
8
1
8
6.3
8.8
1
10
1
10
1
10
6.3
8.8
1
10
1
10
1
10
ns
ns
6.7 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C(1)
SN74AHC86
PARAMETER
MIN
VOL(P)
Quiet output, maximum dynamic VOL
VOL(V)
Quiet output, minimum dynamic VOL
VOH(V)
Quiet output, minimum dynamic VOH
4.4
VIH(D)
High-level dynamic input voltage
3.5
VIL(D)
Low-level dynamic input voltage
(1)
UNIT
TYP
MAX
0.3
0.8
V
–0.3
–0.8
V
V
V
1.5
V
Characteristics are for surface-mount packages only.
6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
No load,
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f = 1 MHz
TYP
18
UNIT
pF
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN74AHC86 SN54AHC86
English Data Sheet: SCLS249
SN74AHC86, SN54AHC86
www.ti.com.cn
ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
7 Parameter Measurement Information
A.
B.
C.
D.
E.
CL includes probe and jig capacitance.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
The outputs are measured one at a time with one input transition per measurement.
All parameters and waveforms are not applicable to all devices.
图 7-1. Load Circuit and Voltage Waveforms
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ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
8 Detailed Description
8.1 Functional Block Diagram
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AHC86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
EVEN-PARITY ELEMENT
=
ODD-PARITY ELEMENT
2k
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
2k + 1
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
图 8-1. Exclusive–OR Logic
8.2 Device Functional Modes
表 8-1. Function Table
(Each Gate)
INPUTS
A
8
OUTPUT
B
Y
L
L
L
L
H
H
H
L
H
H
H
L
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ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, three 2-input AND gates are combined to produce a 4-input AND gate function as shown in
图 9-1. The fourth gate can be used for another application in the system, or the inputs can be grounded and the
channel left unused.
The SN74LV4T08-Q1 is used to directly control the RESET pin of a motor controller. The controller requires four
input signals to all be HIGH before being enabled, and should be disabled in the event that any one signal goes
LOW. The 4-input AND gate function combines the four individual reset signals into a single active-low reset
signal.
9.2 Typical Application
Over Current
Detection
Power Sup ply
Motor Con trol ler
OC
PG
ON/OFF
RESET
OT
Over
Temp
Detection
On/Off Switch
图 9-1. Typical Application Block Diagram
9.2.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions.
The supply voltage sets the electrical characteristics of the device as described in the Electrical Characteristics
section.
The positive voltage supply must be capable of sourcing current equal to the maximum static supply current, ICC,
listed in the Electrical Characteristics, and any transient current required for switching.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SNx4AHC86 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SNx4AHC86 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed
50 pF.
The SNx4AHC86 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOL. When outputting in the HIGH state, the output
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voltage in the equation is defined as the difference between the measured output voltage and the supply voltage
at the VCC pin.
Total power consumption can be calculated using the information provided in the CMOS Power Consumption
and Cpd Calculation application note.
Thermal increase can be calculated using the information provided in the Thermal Characteristics of Standard
Linear and Logic (SLL) Packages and Devices application note.
小心
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.1 Input Considerations
Input signals must cross to be considered a logic LOW, and to be considered a logic HIGH. Do not exceed the
maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SNx4AHC86 (as specified
in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ resistor
value is often used due to these factors.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.2 Output Considerations
The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
10
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9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74AHC1G04-Q1 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω, so that the maximum output current
from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in
MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curves
OC
PG
ON/OFF
OT
RESET
图 9-2. Application Timing Diagram
9.3 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as
shown in the following layout example.
9.4 Layout
9.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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Copyright © 2023 Texas Instruments Incorporated
11
Product Folder Links: SN74AHC86 SN54AHC86
English Data Sheet: SCLS249
SN74AHC86, SN54AHC86
www.ti.com.cn
ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
9.4.1.1 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Unused inputs
tied to VCC
Unused output
left floating
图 9-3. Example Layout for the SNx4AHC86
12
提交文档反馈
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN74AHC86 SN54AHC86
English Data Sheet: SCLS249
SN74AHC86, SN54AHC86
www.ti.com.cn
ZHCSSW5L – OCTOBER 1995 – REVISED OCTOBER 2023
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support (Analog)
10.1.1 Related Documentation
For related documentation, see the following:
•
•
•
•
Texas Instruments, CMOS Power Consumption and Cpd Calculation application note
Texas Instruments, Designing With Logic application note
Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application note
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击通知 进行注册，即可每周接收产品信息更改摘
要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的使用条款。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2023 Texas Instruments Incorporated
13
Product Folder Links: SN74AHC86 SN54AHC86
English Data Sheet: SCLS249
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jul-2025
PACKAGING INFORMATION
Orderable part number
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
5962-9681601Q2A
Active
Production
LCCC (FK) | 20
55 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
59629681601Q2A
SNJ54AHC
86FK
5962-9681601QCA
Active
Production
CDIP (J) | 14
25 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
5962-9681601QC
A
SNJ54AHC86J
5962-9681601QDA
Active
Production
CFP (W) | 14
25 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
5962-9681601QD
A
SNJ54AHC86W
SN74AHC86BQAR
Active
Production
WQFN (BQA) | 14
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86BQAR.A
Active
Production
WQFN (BQA) | 14
3000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86D
Obsolete
Production
SOIC (D) | 14
-
-
Call TI
Call TI
-40 to 125
AHC86
SN74AHC86DBR
Active
Production
SSOP (DB) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86DBR.A
Active
Production
SSOP (DB) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86DGVR
Active
Production
TVSOP (DGV) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86DGVR.A
Active
Production
TVSOP (DGV) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86DR
Active
Production
SOIC (D) | 14
2500 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86DR.A
Active
Production
SOIC (D) | 14
2500 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
AHC86
SN74AHC86DRG4
Active
Production
SOIC (D) | 14
2500 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SN74AHC86DRG4.A
Active
Production
SOIC (D) | 14
2500 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86N
Active
Production
PDIP (N) | 14
25 | TUBE
Yes
NIPDAU
N/A for Pkg Type
-40 to 125
SN74AHC86N
SN74AHC86N.A
Active
Production
PDIP (N) | 14
25 | TUBE
Yes
NIPDAU
N/A for Pkg Type
-40 to 125
SN74AHC86N
SN74AHC86NSR
Active
Production
SOP (NS) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86NSR.A
Active
Production
SOP (NS) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC86
SN74AHC86PW
Obsolete
Production
TSSOP (PW) | 14
-
-
Call TI
Call TI
-40 to 125
HA86
SN74AHC86PWR
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86PWR.A
Active
Production
TSSOP (PW) | 14
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA86
SN74AHC86RGYR
Active
Production
VQFN (RGY) | 14
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA86
SN74AHC86RGYR.A
Active
Production
VQFN (RGY) | 14
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA86
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable part number
(1)
9-Jul-2025
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
SNJ54AHC86FK
Active
Production
LCCC (FK) | 20
55 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
59629681601Q2A
SNJ54AHC
86FK
SNJ54AHC86FK.A
Active
Production
LCCC (FK) | 20
55 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
59629681601Q2A
SNJ54AHC
86FK
SNJ54AHC86J
Active
Production
CDIP (J) | 14
25 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
5962-9681601QC
A
SNJ54AHC86J
SNJ54AHC86J.A
Active
Production
CDIP (J) | 14
25 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
5962-9681601QC
A
SNJ54AHC86J
SNJ54AHC86W
Active
Production
CFP (W) | 14
25 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
5962-9681601QD
A
SNJ54AHC86W
SNJ54AHC86W.A
Active
Production
CFP (W) | 14
25 | TUBE
No
SNPB
N/A for Pkg Type
-55 to 125
5962-9681601QD
A
SNJ54AHC86W
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jul-2025
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHC86, SN74AHC86 :
• Catalog : SN74AHC86
• Military : SN54AHC86
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jul-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
SN74AHC86BQAR
Package Package Pins
Type Drawing
WQFN
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQA
14
3000
180.0
12.4
2.8
3.3
1.1
4.0
12.0
Q1
SN74AHC86DBR
SSOP
DB
14
2000
330.0
16.4
8.35
6.6
2.4
12.0
16.0
Q1
SN74AHC86DGVR
TVSOP
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74AHC86DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHC86DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHC86DRG4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHC86DRG4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHC86NSR
SOP
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74AHC86PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHC86PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHC86RGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jul-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC86BQAR
WQFN
BQA
14
3000
210.0
185.0
35.0
SN74AHC86DBR
SSOP
DB
14
2000
356.0
356.0
35.0
SN74AHC86DGVR
TVSOP
DGV
14
2000
356.0
356.0
35.0
SN74AHC86DR
SOIC
D
14
2500
353.0
353.0
32.0
SN74AHC86DR
SOIC
D
14
2500
356.0
356.0
35.0
SN74AHC86DRG4
SOIC
D
14
2500
356.0
356.0
35.0
SN74AHC86DRG4
SOIC
D
14
2500
353.0
353.0
32.0
SN74AHC86NSR
SOP
NS
14
2000
356.0
356.0
35.0
SN74AHC86PWR
TSSOP
PW
14
2000
353.0
353.0
32.0
SN74AHC86PWR
TSSOP
PW
14
2000
356.0
356.0
35.0
SN74AHC86RGYR
VQFN
RGY
14
3000
356.0
356.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jul-2025
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
NA
5962-9681601Q2A
FK
LCCC
20
55
506.98
12.06
2030
5962-9681601QDA
W
CFP
14
25
506.98
26.16
6220
NA
SN74AHC86N
N
PDIP
14
25
506
13.97
11230
4.32
SN74AHC86N
N
PDIP
14
25
506
13.97
11230
4.32
SN74AHC86N.A
N
PDIP
14
25
506
13.97
11230
4.32
SN74AHC86N.A
N
PDIP
14
25
506
13.97
11230
4.32
SNJ54AHC86FK
FK
LCCC
20
55
506.98
12.06
2030
NA
SNJ54AHC86FK.A
FK
LCCC
20
55
506.98
12.06
2030
NA
SNJ54AHC86W
W
CFP
14
25
506.98
26.16
6220
NA
SNJ54AHC86W.A
W
CFP
14
25
506.98
26.16
6220
NA
Pack Materials-Page 3
PACKAGE OUTLINE
D0014A
SOIC - 1.75 mm max height
SCALE 1.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
6.2
TYP
5.8
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
12X 1.27
14
1
2X
7.62
8.75
8.55
NOTE 3
7
8
B
4.0
3.8
NOTE 4
SEE DETAIL A
14X
0.51
0.31
0.25
C A B
1.75 MAX
0.25
TYP
0.13
0.25
GAGE PLANE
0 -8
0.25
0.10
1.27
0.40
DETAIL A
TYPICAL
4220718/A 09/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
D0014A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
14X (1.55)
SYMM
1
14
14X (0.6)
12X (1.27)
SYMM
8
7
(R0.05)
TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220718/A 09/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0014A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
14X (1.55)
SYMM
1
14
14X (0.6)
12X (1.27)
SYMM
7
8
(5.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4220718/A 09/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
BQA 14
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2.5 x 3, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227145/A
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
BQA0014A
PLASTIC QUAD FLAT PACK-NO LEAD
A
2.6
2.4
B
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.08 C
1.1
0.9
0.05
0.00
(0.2) TYP
2X 0.5
7
8X 0.5
8
6
9
SYMM
2X
2
13
2
PIN 1 ID
(OPTIONAL)
1.6
1.4
15
1
14
SYMM
14X 0.3
0.2
14X 0.5
0.3
0.1
0.05
C A B
C
4224636/A 11/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
BQA0014A
PLASTIC QUAD FLAT PACK-NO LEAD
(2.3)
(1)
2X (0.5)
14
1
2
13
8X (0.5)
(2)
SYMM
2X (0.5)
(1.5)
(2.8)
9
6
14X (0.25)
(Ø0.2) VIA
TYP
7
14X (0.6)
8
SYMM
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
NON-SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
4224636/A 11/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
BQA0014A
PLASTIC QUAD FLAT PACK-NO LEAD
(2.3)
(0.95)
2X (0.5)
1
14
2
13
8X (0.5)
SYMM
(2)
(1.38)
(2.8)
9
6
14X (0.25)
7
8
SYMM
14X (0.6)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
88% PRINTED COVERAGE BY AREA
SCALE: 20X
4224636/A 11/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
DB0014A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
12X 0.65
14
1
2X
6.5
5.9
NOTE 3
3.9
7
8
14X
B
5.6
5.0
NOTE 4
0.38
0.22
0.15
C A B
0.25
0.09
SEE DETAIL A
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4220762/A 05/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0014A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (1.85)
(R0.05) TYP
1
14
14X (0.45)
SYMM
12X (0.65)
7
8
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220762/A 05/2024
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0014A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
14X (1.85)
SYMM
(R0.05) TYP
1
14
14X (0.45)
SYMM
12X (0.65)
7
8
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220762/A 05/2024
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
FK 20
LCCC - 2.03 mm max height
LEADLESS CERAMIC CHIP CARRIER
8.89 x 8.89, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229370\/A\
www.ti.com
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
SCALE 0.900
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID
(OPTIONAL)
A
4X .005 MIN
[0.13]
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL A
SEE DETAIL B
1
14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
( .063)
[1.6]
SOLDER MASK
OPENING
METAL
(R.002 ) TYP
[0.05]
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
PACKAGE OUTLINE
PW0014A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1
2X
5.1
4.9
NOTE 3
3.9
4X (0 -12 )
7
8
14X
B
4.5
4.3
NOTE 4
0.30
0.17
0.1
C A B
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220202/B 12/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0014A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (1.5)
(R0.05) TYP
1
14
14X (0.45)
SYMM
12X (0.65)
8
7
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220202/B 12/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0014A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
14X (1.5)
SYMM
(R0.05) TYP
1
14X (0.45)
14
SYMM
12X (0.65)
8
7
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220202/B 12/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGY 14
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.5 x 3.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4231541/A
www.ti.com
PACKAGE OUTLINE
RGY0014A
VQFN - 1 mm max height
SCALE 3.200
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
3.65
3.35
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
2.05 0.1
2X 1.5
(0.2) TYP
7
8
6
9
2X
2
8X 0.5
2
PIN 1 ID
(OPTIONAL)
13
1
14
14X
0.5
0.3
14X
0.30
0.18
0.1
0.05
C A
B
4219040/A 09/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0014A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.05)
2X (1.5)
SYMM
1
14
14X (0.6)
13
2
14X (0.24)
SYMM
(3.3)
(0.775)
8X (0.5)
9
6
( 0.2) VIA
TYP
7
8
(0.775)
(R0.05) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219040/A 09/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0014A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.5)
4X ( 0.92)
1
14
14X (0.6)
13
2
14X (0.24)
(3.3)
SYMM
(0.56)
8X (0.5)
9
6
METAL
TYP
7
SYMM
(R0.05) TYP
8
(0.56)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4219040/A 09/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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