SN54AHCT00, SN74AHCT00
SCLS229L – OCTOBER 1995 – REVISED MAY 2023
SNx4AHCT00 Quadruple 2-Input Positive-NAND Gates
1 Features
3 Description
•
•
•
•
•
The ’AHCT00 devices perform the Boolean function Y
= A • B or Y = A + B in positive logic.
Operating range of 4.5 V to 5.5 V
Low power consumption, 10-µA maximum ICC
±8-mA output drive at 5 V
Inputs are TTL-voltage compatible
Latch-up performance exceeds 250 mA per JESD
17
PART NUMBER
SN54AHCT00
2 Applications
•
•
•
Package Information(1)
Enable or disable a digital signal
Controlling an indicator LED
Translation between communication modules and
system controllers
SN74AHCT00
(1)
PACKAGE
BODY SIZE (NOM)
J (CDIP, 14)
19.56 mm × 6.67 mm
W (CFP, 14)
9.21 mm × 5.97 mm
FK (LCCC, 20)
8.89 mm × 8.89 mm
D (SOIC , 14)
8.65 mm × 3.91 mm
DB (SSOP, 14)
6.20 mm × 5.30 mm
DGV (TVSOP, 14)
3.60 mm × 4.40 mm
N (PDIP, 14)
19.30 mm × 6.35 mm
NS (SOP, 14)
10.30 mm × 5.30 mm
RGY (QFN, 14)
3.50 mm × 3.50 mm
BQA (WQFN, 14)
3.00 mm × 2.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Gate (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHCT00, SN74AHCT00
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SCLS229L – OCTOBER 1995 – REVISED MAY 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................6
6.7 Noise Characteristics.................................................. 6
6.8 Operating Characteristics........................................... 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
9.3 Power Supply Recommendations.............................13
9.4 Layout....................................................................... 13
10 Device and Documentation Support..........................14
10.1 Documentation Support.......................................... 14
10.2 Receiving Notification of Documentation Updates..14
10.3 Support Resources................................................. 14
10.4 Trademarks............................................................. 14
10.5 Electrostatic Discharge Caution..............................14
10.6 Glossary..................................................................14
11 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (July 2003) to Revision L (May 2023)
Page
• Updated the Features section ........................................................................................................................... 1
• Updated the Applications section ...................................................................................................................... 1
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Added BQA (WQFN) package information.........................................................................................................1
• Added the Package Information table................................................................................................................ 1
• Added the Test and SI table................................................................................................................................8
• Added the Detailed Description sections............................................................................................................ 9
• Added the Application and Implementation sections........................................................................................ 11
2
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5 Pin Configuration and Functions
Figure 5-1. SN54AHCT00 J or W Package,
14-Pin CDIP or CFP
SN74AHCT00 D, DB, DGV, N, NS, or PW Package,
14-Pin SOIC, SSOP, TVSOP, PDIP, SOP, or TSSOP
(Top View)
Figure 5-2. SN74AHCT00 RGY, BQA Package,
14-Pin QFN, WQFN (Transparent Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
1A
1
I
Channel 1, Input A
1B
2
I
Channel 1, Input B
1Y
3
O
Channel 1, Output Y
2A
4
I
Channel 2, Input A
2B
5
I
Channel 2, Input B
2Y
6
O
Channel 2, Output Y
3A
9
O
Channel 3, Output Y
3B
10
I
Channel 3, Input A
3Y
8
I
Channel 3, Input B
4A
12
O
Channel 4, Output Y
4B
13
I
Channel 4, Input A
4Y
11
I
Channel 4, Input B
GND
7
G
Ground
VCC
14
P
Positive Supply
(1)
Signal Types: I = Input, O = Output, I/O = Input or Output, P = Power Supply, G = Ground.
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Figure 5-3. SN54AHCT00 FK Package, 14-Pin LCCC (Top View)
Table 5-2. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
1A
2
I
Channel 1, Input A
1B
3
I
Channel 1, Input B
1Y
4
O
Channel 1, Output Y
2A
6
I
Channel 2, Input A
2B
8
I
Channel 2, Input B
2Y
9
O
Channel 2, Output Y
3A
13
O
Channel 3, Output Y
3B
14
I
Channel 3, Input A
3Y
12
I
Channel 3, Input B
4A
18
O
Channel 4, Output Y
4B
19
I
Channel 4, Input A
4Y
16
I
Channel 4, Input B
NC
1, 5, 7, 11, 15,
17
—
No Connection
GND
10
G
Ground
VCC
20
P
Positive Supply
(1)
4
NO.
Signal Types: I = Input, O = Output, I/O = Input or Output, P = Power Supply, G = Ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
V
range(2)
–0.5
7
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage range(2)
UNIT
IIK
Input clamp current
VI < -0.5 V
-20
mA
IOK
Output clamp current
VO < -0.5 V or VO > VCC + 0.5 V
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
Continuous output current through VCC or GND
Tstg
(1)
(2)
Storage temperature
-65
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V (ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002
(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1))
SN54AHCT00
SN74AHCT00
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
‐8
‐8
mA
IOL
Low-level output current
8
8
mA
Δt/Δv
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
85
°C
(1)
2
0.8
20
‐55
V
2
125
‐40
V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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6.4 Thermal Information
SN74AHCT00
(1)
THERMAL METRIC
R θJA
(1)
D (SOIC)
DB
(SSOP)
DGV
(TVSOP)
N (PDIP
NS (SOP)
PW
(TSSOP)
RGY
(VQFN)
BQA
(WQFN)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
86
96
127
80
76
113
47
88.3
Junction-to-ambient
thermal resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
4.5 V
IOH = -8 mA
IOL = 50 µA
VOL
VI = 5.5 V or GND
ICC
IO = 0
One input at 3.4 V, Other inputs
at VCC or GND
Ci
TYP
4.4
4.5
SN54AHCT00
MAX
VI = VCC or GND
MIN
3.94
0 V to 5.5 V
VI = VCC or GND
(2)
TA= 25°C
MIN
4.5 V
IOL = 8 mA
II
(1)
(2)
VCC
IOH = -50 µA
VOH
ΔICC
TEST CONDITIONS
SN74AHCT00
MAX
MIN
4.4
4.4
3.8
3.8
MAX
V
0.1
0.1
0.1
0.36
0.44
0.44
±0.1
±1
(1)
UNIT
V
±1
µA
5.5 V
2
20
20
µA
5.5 V
1.35
1.5
1.5
mA
10
pF
5V
2
10
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
6.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
(1)
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA= 25°C
MIN
TYP
(1)
5
(1)
5
SN54AHCT00
MAX
6.9
(1)
6.9
(1)
MIN
1
(1)
1
(1)
SN74AHCT00
MAX
MAX
(1)
1
8
(1)
1
8
8
8
MIN
5.5
7.9
1
9
1
9
5.5
7.9
1
9
1
9
UNIT
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.7 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (see (1))
PARAMETER
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.4
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.4
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
6
SN74AHCT00
MIN
4.5
V
2
V
0.8
V
Characteristics are for surface-mount packages only.
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6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
TYP
UNIT
No load,
10.5
pF
f = 1 MHz
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7 Parameter Measurement Information
A.
B.
C.
D.
E.
CL includes probe and jig capacitance.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
The outputs are measured one at a time with one input transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
Table 7-1. Test and SI
8
TEST
S1
tPLH/tPHL
Open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
Open Drain
VCC
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8 Detailed Description
8.1 Overview
This device contains four independent 2-input NAND Gates. Each gate performs the Boolean function Y = A ● B
in positive logic.
8.2 Functional Block Diagram
xA
xY
xB
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 TTL-Compatible CMOS Inputs
This device includes TTL-compatible CMOS inputs. These inputs are specifically designed to interface with TTL
logic devices by having a reduced input voltage threshold.
TTL-compatible CMOS inputs are high impedance and are typically modeled as a resistor in parallel with
the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the
maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given
in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
TTL-compatible CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in the Implications of Slow or Floating CMOS Inputs application report.
Do not leave TTL-compatible CMOS inputs floating at any time during operation. Unused inputs must be
terminated at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down
resistor can be added to provide a valid input voltage during these times. The resistor value will depend on
multiple factors; however, a 10-kΩ resistor is recommended and will typically meet all requirements.
8.3.3 Clamp Diode Structure
As Figure 8-1 shows, the outputs to this device have both positive and negative clamping diodes, and the inputs
to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
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Device
VCC
+IOK
Input
Output
Logic
-IIK
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
(Each Gate)
INPUTS
10
OUTPUT
A
B
Y
H
H
L
L
X
H
X
L
H
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, two 2-input NAND gates are used to create an active-low SR latch as shown in Figure 9-1.
The two additional gates can be used for a second SR latch, or the inputs can be grounded and both channels
left unused.
The AHCT00 is used to drive the tamper indicator LED and provide one bit of data to the system controller.
When the tamper switch outputs LOW, the output Q becomes HIGH. This output remains HIGH until the system
controller addresses the event and sends a LOW signal to the R input which returns the Q output back to LOW.
The inputs of this active-low SR latch can often be driven by open-drain outputs which can produce slow
input transition rates when they transition from LOW to Hi-Z. This makes the AHCT00 ideal for the application
because it has Schmitt-trigger inputs that do not have input transition rate requirements.
9.2 Typical Application
System
Controller
R1
R
Tamper
Switch
Q
S
R2
Tamper
Indicator
Figure 9-1. Typical Application Block Diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the AHCT00 plus the maximum static supply current, ICC, listed in the Electrical Characteristics, and
any transient current required for switching. The logic device can only source as much current that is provided by
the positive supply source. Be sure to not exceed the maximum total current through VCC listed in the Absolute
Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the AHCT00
plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient current required
for switching. The logic device can only sink as much current that can be sunk into its ground connection. Be
sure to not exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
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The AHCT00 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the
data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50
pF.
The AHCT00 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and current
defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output
voltage in the equation is defined as the difference between the measured output voltage and the supply voltage
at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the AHCT00 (as specified in
the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ resistor value
is often used due to these factors.
The AHCT00 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
12
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2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the AHCT00 to
one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curves
R
S
Q
Figure 9-2. Application Timing Diagram
9.3 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as
shown in Layout Example.
9.4 Layout
9.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
9.4.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Unused inputs
tied to VCC
Unused output
left floating
Figure 9-3. Example Layout for the AHCT00
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, CMOS Power Consumption and Cpd Calculation application note
Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application note
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN54AHCT00 SN74AHCT00
PACKAGE OPTION ADDENDUM
www.ti.com
25-May-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9682301Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629682301Q2A
SNJ54AHCT
00FK
5962-9682301QCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9682301QC
A
SNJ54AHCT00J
5962-9682301QDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9682301QD
A
SNJ54AHCT00W
SN74AHCT00BQAR
ACTIVE
WQFN
BQA
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT00
Samples
SN74AHCT00D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT00
Samples
SN74AHCT00DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HB00
Samples
SN74AHCT00DGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HB00
Samples
SN74AHCT00DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT00
Samples
SN74AHCT00DRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT00
Samples
SN74AHCT00N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74AHCT00N
Samples
SN74AHCT00NE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74AHCT00N
Samples
SN74AHCT00NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT00
Samples
SN74AHCT00PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HB00
Samples
SN74AHCT00RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
HB00
Samples
SNJ54AHCT00FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629682301Q2A
SNJ54AHCT
00FK
SNJ54AHCT00J
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9682301QC
A
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
25-May-2023
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SNJ54AHCT00J
SNJ54AHCT00W
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9682301QD
A
SNJ54AHCT00W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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