SN74AHCT138DBR

SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS266M − DECEMBER 1995 − REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible D Designed Specifically for High-Speed D Memory Decoders and Data-Transmission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception 15 3 14 4 13 5 6 12 11 7 10 8 9 B C G2A G2B G1 Y7 1 16 B A NC VCC Y0 VCC VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 SN54AHCT138 . . . FK PACKAGE (TOP VIEW) C G2A NC G2B G1 15 Y0 14 Y1 2 3 13 Y2 12 Y3 4 5 11 Y4 10 Y5 6 7 8 9 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 NC Y3 Y4 Y7 GND NC Y6 Y5 2 16 Y6 1 A SN74AHCT138 . . . RGY PACKAGE (TOP VIEW) SN54AHCT138 . . . J OR W PACKAGE SN74AHCT138 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y7 GND JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) GND D D Latch-Up Performance Exceeds 250 mA Per NC − No internal connection description/ordering information The ’AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. ORDERING INFORMATION Tape and reel SN74AHCT138RGYR HB138 PDIP − N Tube SN74AHCT138N SN74AHCT138N Tube SN74AHCT138D Tape and reel SN74AHCT138DR SOP − NS Tape and reel SN74AHCT138NSR AHCT138 SSOP − DB Tape and reel SN74AHCT138DBR HB138 Tube SN74AHCT138PW Tape and reel SN74AHCT138PWR TVSOP − DGV Tape and reel SN74AHCT138DGVR HB138 CDIP − J Tube SNJ54AHCT138J SNJ54AHCT138J CFP − W Tube SNJ54AHCT138W SNJ54AHCT138W LCCC − FK Tube SNJ54AHCT138FK SNJ54AHCT138FK TSSOP − PW −55°C 55 C to 125 125°C C † TOP-SIDE MARKING QFN − RGY SOIC − D −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA AHCT138 HB138 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS266M − DECEMBER 1995 − REVISED JULY 2003 description/ordering information (continued) The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. FUNCTION TABLE SELECT INPUTS ENABLE INPUTS OUTPUTS G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 X H X X X X H H H H H H H Y7 H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L logic diagram (positive logic) 15 Y0 A 1 14 Y1 13 Select Inputs B Y2 2 12 Y3 11 3 Data Outputs Y4 C 10 Y5 9 Y6 4 G2A Enable Inputs G2B 7 5 6 G1 Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y7 SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS266M − DECEMBER 1995 − REVISED JULY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 4) SN54AHCT138 SN74AHCT138 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 0 5.5 VO Output voltage 0 VCC IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature 2 2 0.8 V V 0.8 V 0 5.5 V 0 VCC −8 −55 UNIT −8 V mA 8 8 mA 20 20 ns/V 85 °C 125 −40 NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS266M − DECEMBER 1995 − REVISED JULY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC IOH = −50 mA 45V 4.5 IOH = −8 mA IOL = 50 mA TA = 25°C MIN TYP 4.4 4.5 3.94 45V 4.5 IOL = 8 mA SN54AHCT138 MAX MIN MAX SN74AHCT138 MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.1 0.36 0.5 0.44 V II VI = 5.5 V or GND ±0.1 ±1* ±1 mA ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 mA ΔICC† One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA Ci VI = VCC or GND 10 pF 0 V to 5.5 V 5V 2 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. † This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V . CC switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL * FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A B, A, B C Any Y CL = 15 pF G1 Any Y CL = 15 pF G2A G2B G2A, Any Y CL = 15 pF A B, B C A, Any Y CL = 50 pF G1 Any Y CL = 50 pF G2A G2B G2A, Any Y CL = 50 pF TA = 25°C MIN SN54AHCT138 SN74AHCT138 TYP MAX MIN MAX MIN MAX 7.6* 10.4* 1* 12* 1 12 7.6* 10.4* 1* 12* 1 12 6.6* 9.1* 1* 10.5* 1 10.5 6.6* 9.1* 1* 10.5* 1 10.5 7* 9.6* 1* 11* 1 11 7* 9.6* 1* 11* 1 11 8.1 11.4 1 13 1 13 8.1 11.4 1 13 1 13 7.1 10.1 1 11.5 1 11.5 7.1 10.1 1 11.5 1 11.5 7.5 10.6 1 12 1 12 7.5 10.6 1 12 1 12 TEST CONDITIONS TYP UNIT ns ns ns ns ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 14 UNIT pF SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS266M − DECEMBER 1995 − REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH In-Phase Output 50% VCC tPHL Out-of-Phase Output 50% VCC VOL 3V Output Control Output Waveform 1 S1 at VCC (see Note B) 1.5 V 0V tPZL 50% VCC tPLZ ≈VCC 50% VCC tPZH tPLH VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS266M − DECEMBER 1995 − REVISED JULY 2003 APPLICATION INFORMATION SN74AHCT138 BIN/OCT 1 2 3 VCC 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 0 1 2 3 4 5 6 7 SN74AHCT138 BIN/OCT 1 A0 2 A1 3 A2 1 2 2 4 6 A3 0 1 3 & 4 4 A4 EN 5 5 6 7 15 14 13 12 11 10 9 7 8 9 10 11 12 13 14 15 SN74AHCT138 BIN/OCT 1 2 3 6 0 1 1 2 2 4 3 & 4 4 5 EN 5 6 7 Figure 2. 24-Bit Decoding Scheme 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 14 13 12 11 10 9 7 16 17 18 19 20 21 22 23 SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS266M − DECEMBER 1995 − REVISED JULY 2003 APPLICATION INFORMATION SN74AHCT138 BIN/OCT 1 A0 2 A1 3 A2 1 1 2 2 4 6 VCC 0 3 & 4 4 A3 EN 5 A4 5 6 7 15 14 13 12 11 10 9 7 0 1 2 3 4 5 6 7 SN74AHCT138 BIN/OCT 1 2 3 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 8 9 10 11 12 13 14 15 SN74AHCT138 BIN/OCT 1 2 3 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 16 17 18 19 20 21 22 23 SN74AHCT138 BIN/OCT 1 2 3 6 0 1 1 2 2 4 3 & 4 4 5 EN 5 6 7 15 14 13 12 11 10 9 7 24 25 26 27 28 29 30 31 Figure 3. 32-Bit Decoding Scheme POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9851701Q2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629851701Q2A SNJ54AHCT 138FK 5962-9851701QEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9851701QE A SNJ54AHCT138J 5962-9851701QFA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9851701QF A SNJ54AHCT138W SN74AHCT138D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT138 Samples SN74AHCT138DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB138 Samples SN74AHCT138DGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB138 Samples SN74AHCT138DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT138 Samples SN74AHCT138N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AHCT138N Samples SN74AHCT138NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT138 Samples SN74AHCT138PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB138 Samples SN74AHCT138PWE4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB138 Samples SN74AHCT138PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB138 Samples SN74AHCT138PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HB138 Samples SN74AHCT138RGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 HB138 Samples SNJ54AHCT138FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629851701Q2A SNJ54AHCT 138FK SNJ54AHCT138J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9851701QE A Addendum-Page 1 Samples Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SNJ54AHCT138J SNJ54AHCT138W ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9851701QF A SNJ54AHCT138W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of