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SN74AHCT16373DL

SN74AHCT16373DL

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SSOP48

  • 描述:

    IC 16BIT TRANSP D LATCH 48-SSOP

  • 数据手册
  • 价格&库存
SN74AHCT16373DL 数据手册
Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 SNx4AHCT16373 16-Bit Transparent D-Type Latches With 3-State Outputs 1 Features 2 Applications • • • • • • 1 • • • • • • • Members of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Process Inputs are TTL-Voltage Compatible Distributed VCC and GND Pins Minimize HighSpeed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include: – Plastic Shrink Small-Outline (DL) Package – Thin Shrink Small-Outline (DGG) Package – Thin Very Small-Outline (DGV) Package – 80-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings Wearable Health and Fitness Devices Toys PCs and Notebooks Power Infrastructures Servers 3 Description The SNxAHCT16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. Device Information(1) PART NUMBER SNx4AHC16373 PACKAGE BODY SIZE (NOM) TSSOP (48) 12.50 mm × 6.10 mm TVSOP (48) 9.70 mm × 4.40 mm SSOP (48) 15.88 mm × 7.49 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic 1OE 2OE 1LE 2LE C1 1D1 1D To Seven Other Channels C1 1Q1 2D1 1D 2Q1 To Seven Other Channels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 5 5 5 6 6 6 7 7 7 8 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... Noise Characteristics ................................................ Operating Characteristics.......................................... Typical Characteristics ............................................ Parameter Measurement Information .................. 9 9 Detailed Description ............................................ 10 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ 10 10 11 11 10 Application and Implementation........................ 12 10.1 Application Information.......................................... 12 10.2 Typical Application ............................................... 12 11 Power Supply Recommendations ..................... 13 12 Layout................................................................... 13 12.1 Layout Guidelines ................................................. 13 12.2 Layout Example .................................................... 13 13 Device and Documentation Support ................. 14 13.1 13.2 13.3 13.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 14 14 14 14 14 Mechanical, Packaging, and Orderable Information ........................................................... 14 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (January 2000) to Revision I Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Added Applications. ................................................................................................................................................................ 1 • Added Pin Functions table...................................................................................................................................................... 3 • Added Handling Ratings table. ............................................................................................................................................... 5 • Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5 • Added Thermal Information table. .......................................................................................................................................... 6 • Added –40°C to 125°C for SN74AHCT16373 in Electrical Characteristics table................................................................... 6 • Added TA = –40°C to 125°C for SN74AHCT16373 in the Timing Requirements table.......................................................... 6 • Added TA = –40°C to 125°C for SN74AHCT16373 in the Switching Characteristics table.................................................... 7 • Added Typical Characteristics. ............................................................................................................................................... 8 • Added Detailed Description section...................................................................................................................................... 10 • Added Application and Implementation section.................................................................................................................... 12 • Added Power Supply Recommendations and Layout sections............................................................................................ 13 2 Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT16373 SN74AHCT16373 SN54AHCT16373, SN74AHCT16373 www.ti.com SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 6 Pin Configuration and Functions SN54AHCT16373 . . . WD PACKAGE SN74AHCT16373 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE Pin Functions PIN I/O DESCRIPTION 1OE I Output Enable 1 1Q1 O 1Q1 Output 1Q2 O 1Q2 Output GND — Ground Pin 5 1Q3 O 1Q3 Output 6 1Q4 O 1Q4 Output 7 VCC — Power Pin 8 1Q5 O 1Q5 Output 9 1Q6 O 1Q6 Output 10 GND — Ground Pin 11 1Q7 O 1Q7 Output 12 1Q8 O 1Q8 Output 13 2Q1 O 2Q1 Output 14 2Q2 O 2Q2 Output 15 GND — Ground Pin 16 2Q3 O 2Q3 Output 17 2Q4 O 2Q4 Output 18 VCC — Power Pin NO. NAME 1 2 3 4 Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN54AHCT16373 SN74AHCT16373 3 SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 www.ti.com Pin Functions (continued) PIN 4 I/O DESCRIPTION 2Q5 O 2Q5 Output 2Q6 O 2Q6 Output 21 GND — Ground Pin 22 2Q7 O 2Q7 Output 23 2Q8 O 2Q8 Output 24 2OE I Output Enable 2 25 2LE I Latch Enable 2 26 2D8 I 2D8 Input 27 2D7 I 2D7 Input 28 GND — 29 2D6 I 2D6 Input 30 2D5 I 2D5 Input 31 VCC — Power Pin 32 2D4 I 2D4 Input 33 2D3 I 2D3 Input 34 GND — 35 2D2 I 2D2 Input 36 2D1 I 2D1 Input 37 1D8 I 1D8 Input 38 1D7 I 1D7 Input 39 GND — 40 1D6 I 1D6 Input 41 1D5 I 1D5 Input 42 VCC — Power Pin 43 1D4 I 1D4 Input 44 1D3 I 1D3 Input 45 GND — 46 1D2 I 1D2 Input 47 1D1 I 1D1 Input 48 1LE I Latch Enable 1 NO. NAME 19 20 Submit Documentation Feedback Ground Pin Ground Pin Ground Pin Ground Pin Copyright © 2000–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT16373 SN74AHCT16373 SN54AHCT16373, SN74AHCT16373 www.ti.com SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 7 UNIT V (2) –0.5 7 V –0.5 VCC + 0.5 VI Input voltage range VO Output voltage range (2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±75 mA Continuous current through VCC or GND (1) (2) V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT °C –65 150 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) SN54AHCT16373 (2) SN74AHCT16373 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 0 5.5 VO Output voltage 0 VCC IOH High-level output current –8 –8 IOL Low-level output current 8 8 mA ∆t/∆v Input transition rise or fall rate 20 20 ns/V TA Operating free-air temperature 125 °C (1) (2) 2 2 0.8 –55 V 125 V 0.8 V 0 5.5 V 0 VCC V –40 mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Product Preview Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN54AHCT16373 SN74AHCT16373 5 SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 www.ti.com 7.4 Thermal Information SN74AHCT16373 THERMAL METRIC (1) DGG DGV DL UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 69.9 80.9 61.4 RθJC(top) Junction-to-case (top) thermal resistance 24.2 32.8 31.4 RθJB Junction-to-board thermal resistance 26.9 44.0 33.2 ψJT Junction-to-top characterization parameter 1.9 3.3 9.0 ψJB Junction-to-board characterization parameter 36.6 43.4 32.9 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH 4.5 V IOH = –8 mA IOL = 50 µA VOL MIN TYP 4.4 4.5 MAX 3.94 4.5 V IOL = 8 mA SN54AHCT16373 (1) TA = 25°C VCC MIN –40°C to 85°C SN74AHCT16373 MAX MIN –40°C to 125°C SN74AHCT16373 MAX MIN 4.4 4.4 4.4 3.8 3.8 3.8 UNIT MAX V 0.1 0.1 0.1 0.1 0.36 0.44 0.44 0.44 V II VI = VCC or GND 0 V to 5.5 V ±0.1 ±1 (2) ±1 ±1 µA IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 40 µA ΔICC (3) One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 1.5 mA Ci VI = VCC or GND 5V 2.5 Co VO = VCC or GND 5V 4.5 (1) (2) (3) 10 10 pF pF Product Preview On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. 7.6 Timing Requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) TA = 25°C MIN MAX SN54AHCT16373 (1) MIN MAX SN74AHCT16373 MIN MAX TA = –40°C to 125°C SN74AHCT16373 MIN UNIT MAX tw Pulse duration, LE high 6.5 6.5 6.5 6.5 ns tsu Setup time, data before LE↓ 1.5 1.5 1.5 1.5 ns th Hold time, data after LE↓ 3.5 3.5 3.5 3.5 ns (1) 6 Product Preview Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT16373 SN74AHCT16373 SN54AHCT16373, SN74AHCT16373 www.ti.com SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 7.7 Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (OUTPUT) TO (INPUT) MIN tPLH D Q CL = 15 pF tPHL tPLH LE Q CL = 15 pF tPHL tPZH OE Q CL = 15 pF tPZL tPHZ Q CL = 15 pF tPLH D Q CL = 50 pF tPHL tPLH LE Q CL = 50 pF tPHL tPZH OE Q CL = 50 pF tPZL tPHZ OE Q CL = 50 pF tPLZ tsk(o) (1) (2) (3) CL = 50 pF SN74AHCT16373 SN74AHCT16373 TA = –40°C to 125°C UNIT TYP MAX MIN MAX MIN MAX MIN MAX 5.1 (2) 8.5 (2) 1 (2) 9.5 (2) 1 9.5 1 10.5 (2) (2) (2) 9.5 (2) 1 9.5 1 10.5 5.1 8.5 1 ns 5 (2) 8.5 (2) 1 (2) 9.5 (2) 1 9.5 1 10.5 5 (2) 8.5 (2) 1 (2) 9.5 (2) 1 9.5 1 10.5 5 (2) 9.5 (2) 1 (2) 10.5 (2) 1 10.5 1 11.1 5 (2) 9.5 (2) 1 (2) 10.5 (2) 1 10.5 1 11.1 (2) (2) (2) (2) 6 OE tPLZ SN54AHCT16373 (1) TA = 25°C LOAD CAPACITANCE 10.2 1 11 ns ns 1 11 1 11.6 6.8 (2) 10.2 (2) 1 (2) 11 (2) 1 11 1 11.6 5.9 9.5 1 10.5 1 10.5 1 11.5 5.9 9.5 1 10.5 1 10.5 1 11.5 6.4 9.5 1 10.5 1 10.5 1 11.5 5.9 9.5 1 10.5 1 10.5 1 11.5 6 10.5 1 11.5 1 11.5 1 12.1 6 10.5 1 11.5 1 11.5 1 12.1 6.8 11.2 1 12 1 12 1 12.6 7.8 11.2 1 12 1 12 1 12.6 ns ns ns ns ns 1 (3) 1 1 ns Product Preview On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. 7.8 Noise Characteristics VCC = 5 V, CL = 50 pF, TA = 25°C (1) SN74AHCT16373 PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.32 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.1 –0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.7 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) V 2 V 0.8 V Characteristics are for surface-mount packages only. 7.9 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance Copyright © 2000–2014, Texas Instruments Incorporated TEST CONDITIONS No load, f = 1 MHz TYP UNIT 22 Submit Documentation Feedback Product Folder Links: SN54AHCT16373 SN74AHCT16373 pF 7 SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 www.ti.com 7.10 Typical Characteristics 7 6 TPD (ns) 5 4 3 2 1 TPD in ns 0 -100 -50 0 50 Temperature (qC) 100 150 D001 Figure 1. TPD vs Temperature 8 Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT16373 SN74AHCT16373 SN54AHCT16373, SN74AHCT16373 www.ti.com SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 8 Parameter Measurement Information From Output Under Test Test Point From Output Under Test RL = 1 kΩ S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPLZ tPZL ≈VCC 50% VCC VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuit and Voltage Waveforms Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN54AHCT16373 SN74AHCT16373 9 SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 www.ti.com 9 Detailed Description 9.1 Overview The SNxAHCT16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, IO ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagrams 1OE 2OE 1LE 2LE C1 C1 1D1 1Q1 1D To Seven Other Channels 1D 2D1 2Q1 To Seven Other Channels Figure 3. Logic Diagram (Positive Logic) 10 Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT16373 SN74AHCT16373 SN54AHCT16373, SN74AHCT16373 www.ti.com SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 Functional Block Diagrams (continued) 1OE 1EN 1LE C3 2EN 2OE 2LE C4 1D1 3D 1 1Q1 1D2 1Q2 1D3 1Q3 1D4 1Q4 1D5 1Q5 1D6 1Q6 1D7 1Q7 1D8 1Q8 2D1 2 4D 2Q1 2D2 2Q2 2D3 2Q3 2D4 2Q4 2D5 2Q5 2D6 2Q6 2D7 2Q7 2D8 2Q8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Figure 4. Logic Symbol 9.3 Feature Description • • TTL inputs – Lowered switching threshold allows up translation from 3.3 V to 5 V Slow edges reduce output ringing 9.4 Device Functional Modes Table 1. Function Table (Each 8-bit Latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN54AHCT16373 SN74AHCT16373 11 SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 www.ti.com 10 Application and Implementation 10.1 Application Information The SN74AHCT16373 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V VIL and 2-V VIH. This feature makes it ideal for translating up from 3.3 V to 5 V. Figure 6 shows this type of translation. 10.2 Typical Application Regulated 5 V Regulated 3.3 V OE VCC LE 1D 1Q µC or 5 V µC System Logic System Logic 8D 8Q LEDs GND Figure 5. Typical Application Schematic 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended input conditions – Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC 2. Recommend output conditions – Load currents should not exceed 25 mA per output and 75 mA total for the part – Outputs should not be pulled above VCC 12 Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT16373 SN74AHCT16373 SN54AHCT16373, SN74AHCT16373 www.ti.com SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 Typical Application (continued) 10.2.3 Application Curves Figure 6. Up Translation 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input-AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 7 are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float outputs unless the part is a transceiver. 12.2 Layout Example Vcc Input Unused Input Output Output Unused Input Input Figure 7. Layout Diagram Copyright © 2000–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN54AHCT16373 SN74AHCT16373 13 SN54AHCT16373, SN74AHCT16373 SCLS336I – JANUARY 2000 – REVISED AUGUST 2014 www.ti.com 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54AHCT16373 Click here Click here Click here Click here Click here SN74AHCT16373 Click here Click here Click here Click here Click here 13.2 Trademarks Widebus is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Documentation Feedback Copyright © 2000–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT16373 SN74AHCT16373 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74AHCT16373DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT16373 Samples SN74AHCT16373DGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HF373 Samples SN74AHCT16373DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT16373 Samples SN74AHCT16373DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT16373 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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