SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
D
D
D
D
D
SN54AHCT174 . . . J OR W PACKAGE
SN74AHCT174 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Contain Six Flip-Flops With Single-Rail
Outputs
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
CLR
1Q
1D
2D
2Q
3D
3Q
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
6Q
6D
5D
5Q
4D
4Q
CLK
SN54AHCT174 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
VCC
6Q
description
These positive-edge-triggered D-type flip-flops
have a direct clear (CLR) input.
1D
2D
NC
2Q
3D
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
6D
5D
NC
5Q
4D
3Q
GND
NC
CLK
4Q
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
4
NC – No internal connection
ORDERING INFORMATION
PDIP – N
–55°C to 125°C
TOP-SIDE
MARKING
Tube
SN74AHCT174N
Tube
SN74AHCT174D
Tape and reel
SN74AHCT174DR
SOP – NS
Tape and reel
SN74AHCT174NSR
AHCT174
SSOP – DB
Tape and reel
SN74AHCT174DBR
HB174
TSSOP – PW
Tape and reel
SN74AHCT174PWR
HB174
TVSOP – DGV
Tape and reel
SN74AHCT174DGVR
HB174
CDIP – J
Tube
SNJ54AHCT174J
SNJ54AHCT174J
CFP – W
Tube
SNJ54AHCT174W
SNJ54AHCT174W
LCCC – FK
Tube
SNJ54AHCT174FK
SNJ54AHCT174FK
SOIC – D
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74AHCT174N
AHCT174
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
CLK
D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
logic diagram (positive logic)
CLR
CLK
1D
1
9
3
1D
C1
2
1Q
R
To Five Other Channels
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
recommended operating conditions (see Note 3)
SN54AHCT174
SN74AHCT174
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
V
Input voltage
0
5.5
0
5.5
V
VO
IOH
Output voltage
0
0
VCC
–8
V
High-level output current
VCC
–8
mA
IOL
∆t/∆v
Low-level output current
8
8
mA
20
20
ns/V
High-level input voltage
2
2
0.8
Input transition rise or fall time
V
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
ICC
∆ICC†
TEST CONDITIONS
VCC
IOH = –50 mA
MIN
4.4
45V
4.5
IOH = –8 mA
IOL = 50 mA
TA = 25°C
TYP
MAX
4.5
3.94
MAX
SN74AHCT174
MIN
4.4
4.4
3.8
3.8
MAX
UNIT
V
0.1
0.1
0.36
0.44
0.44
±0.1
±1*
±1
mA
5.5 V
4
40
40
mA
5.5 V
1.35
1.5
1.5
0 V to 5.5 V
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
MIN
0.1
45V
4.5
IOL = 8 mA
VI = 5.5 V or GND
SN54AHCT174
Ci
VI = VCC or GND
5V
2
10
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
† This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
10
V
m
A
pF
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
S t time
Setup
ti
b
before
f
CLK↑
th
Hold time, data after CLK↑
SN54AHCT174
MIN
MAX
SN74AHCT174
MIN
CLR low
5
5
5
CLK high or low
5
5
5
Data
CLR inactive
5
5
5
3.5
3.5
3.5
0
0
0
MAX
UNIT
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
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3
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
fmax
tPHL
tPLH
MIN
TA = 25°C
TYP
MAX
SN54AHCT174
MIN
SN74AHCT174
MAX
MIN
CL = 15 pF
100**
135**
80**
80
CL = 50 pF
80
115
65
65
10.4**
1**
13**
1
13
5.8**
7.8**
1**
9**
1
9
5.8**
7.8**
1**
9**
1
9
8.1
11.4
1
13
1
13
6.3
8.8
1
10
1
10
6.3
8.8
1
10
1
10
tsk(o)
CL = 50 pF
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
1***
tPLH
tPHL
Any Q
CL = 15 pF
CLK
Any Q
CL = 15 pF
CLR
Any Q
CL = 50 pF
CLK
Any Q
CL = 50 pF
UNIT
MHz
7.6**
tPHL
tPHL
CLR
MAX
1
ns
ns
ns
ns
ns
noise characteristics VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)
SN74AHCT174
PARAMETER
MIN
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
4
High-level dynamic input voltage
2
Quiet output, minimum dynamic VOL
TYP
MAX
UNIT
0.8
V
–0.8
V
VIL(D)
Low-level dynamic input voltage
NOTE 4: Characteristics are for surface-mount packages only.
V
V
0.8
V
TYP
UNIT
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
28
pF
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AHCT174D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT174
SN74AHCT174DBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HB174
SN74AHCT174DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT174
SN74AHCT174N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74AHCT174N
SN74AHCT174NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT174
SN74AHCT174PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HB174
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of