Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
SN74AHCT1G04
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
SN74AHCT1G04 Single Inverter Gate
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
1
Operating Range 4.5-V to 5.5-V
Max tpd of 7.5 ns at 5-V
Low Power Consumption, 10-μA Max ICC
±8-mA Output Drive at 5-V
Inputs are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Notebook PCs
Electronic Points of Sale
Patient Monitoring
Motor Controls: AC Induction
Network Switches
Tests
3 Description
The SN74AHCT1G04 contains one gate. The device
performs the Boolean function Y = A.
Device Information(1)
PART NUMBER
SN74AHCT1G04
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm x 1.60 mm
SC-70 (5)
2.00 mm x 1.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
A
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHCT1G04
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
5
5
5
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
7
7
7
7
10 Application and Implementation.......................... 8
10.1 Application Information............................................ 8
10.2 Typical Application ................................................. 8
11 Power Supply Recommendations ....................... 9
12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
12.2 Layout Example .................................................... 10
13 Device and Documentation Support ................. 10
13.1 Trademarks ........................................................... 10
13.2 Electrostatic Discharge Caution ............................ 10
13.3 Glossary ................................................................ 10
14 Mechanical, Packaging, and Orderable
Information ........................................................... 10
5 Revision History
Changes from Revision O (October 2013) to Revision P
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. .......................................... 4
2
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
SN74AHCT1G04
www.ti.com
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
6 Pin Configuration and Functions
DBV OR DCK PACKAGE
(TOP VIEW)
NC
A
GND
1
5
VCC
4
Y
2
3
NC – No internal connection
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
NC
—
2
A
I
No Connection
3
GND
—
Ground Pin
Input A
4
Y
O
Output Y
5
VCC
—
Power Pin
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
3
SN74AHCT1G04
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
Storage temperature range
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions() is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
1500
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1)
MIN
MAX
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level Input voltage
0.8
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
–8
IOL
Low-level output current
8
mA
Δt/Δv
Input Transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
V
2
V
–40
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004)
7.4 Thermal Information
SN74AHCT1G04
THERMAL METRIC (1)
DBV
DCK
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
231.3
287.6
RθJC(top)
Junction-to-case (top) thermal resistance
119.9
97.7
RθJB
Junction-to-board thermal resistance
60.6
65.
ψJT
Junction-to-top characterization parameter
17.8
2.0
ψJB
Junction-to-board characterization parameter
60.1
64.2
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
SN74AHCT1G04
www.ti.com
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
II
ICC
ΔICC (1)
Ci
(1)
TEST CONDITIONS
IOH = –50 µA
TA = 25°C
VCC
4.5 V
IOH = –8 mA
IOL = 50 µA
MIN
TYP
4.4
4.5
–40°C to 85°C
MAX
3.94
4.5 V
IOL = 8 mA
MIN
–40°C to 125°C
MAX
MIN
4.4
4.4
3.8
3.8
UNIT
MAX
V
0.1
0.1
0.1
0.36
0.44
0.44
V
VI = 5.5 V or GND
0 V to
5.5 V
±0.1
±1
±1
µA
VI = VCC or
GND,
5.5 V
1
10
10
µA
5.5 V
1.35
1.5
1.5
mA
10
10
pF
IO = 0
One input at 3.4 V, Other
Inputs at VCC or GND
VI = VCC or GND
5V
4
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
7.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
–40°C to 85°C
TYP
MIN
MAX
MAX
–40°C to 125°C
MIN
UNIT
MAX
4.7
1
7.5
1
8
4.7
1
7.5
1
8
5.5
1
8.5
1
9
5.5
1
8.5
1
9
ns
ns
7.7 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
TYP
14
UNIT
pF
7.8 Typical Characteristics
6
5
TPD (ns)
4
3
2
1
TPD in ns
0
-100
-50
0
50
Temperature (qC)
100
150
D001
Figure 1. TPD vs Temperature
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
5
SN74AHCT1G04
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
www.ti.com
8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
3V
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit And Voltage Waveforms
6
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
SN74AHCT1G04
www.ti.com
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
9 Detailed Description
9.1 Overview
The SN74AHCT1G04 device contains one inverter. This device has TTL input levels that allow up translation
from 3.3 V to 5 V.
9.2 Functional Block Diagram
A
Y
Figure 3. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
•
•
VCC is optimized at 5 V
Allows up voltage translation from 3.3 V to 5 V
– Inputs accept VIH levels of 2 V
Slow edge rates minimize output ringing
Inputs are TTL-Voltage compatible
9.4 Device Functional Modes
Table 1. Function Table
INPUT
A
OUTPUT
Y
H
L
L
H
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
7
SN74AHCT1G04
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
SN74AHCT1G04 is a low-drive CMOS device that can be used for a multitude of inverting type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8 V VILand 2 V VIH.
This feature makes it Ideal for translating up from 3.3 V to 5 V. Figure 5 shows this type of translation.
10.2 Typical Application
3.3-V accessory
5-V regulated
0.1 µF
Figure 4. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions (1) table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions (1) table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
(1)
8
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004)
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
SN74AHCT1G04
www.ti.com
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
Typical Application (continued)
10.2.3 Application Curves
Figure 5. 3.3-V to 5-V Translation
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions (1) table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
9
SN74AHCT1G04
SCLS319P – MARCH 1996 – REVISED DECEMBER 2014
www.ti.com
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
Submit Documentation Feedback
Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHCT1G04
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74AHCT1G04DBVRE4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
B04G
74AHCT1G04DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
B04G
74AHCT1G04DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
B04G
74AHCT1G04DCKRE4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BC3
74AHCT1G04DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BC3
74AHCT1G04DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BC3
SN74AHCT1G04DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(B043, B04G, B04J,
B04L, B04S)
SN74AHCT1G04DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(B043, B04G, B04J,
B04L, B04S)
SN74AHCT1G04DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(BC3, BCG, BCJ, BC
L, BCS)
SN74AHCT1G04DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(BC3, BCG, BCJ, BC
L, BCS)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
