SN74AHCT1G125DBVR

 
  
    
  SCLS378L − AUGUST 1997 − REVISED JUNE 2005 D D D D D Inputs Are TTL-Voltage Compatible D Latch-Up Performance Exceeds 250 mA Per Operating Range of 4.5 V to 5.5 V Max tpd of 6 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V JESD 17 DBV PACKAGE (TOP VIEW) OE 1 A 2 GND 3 DCK PACKAGE (TOP VIEW) VCC 5 OE 1 A 2 GND 3 DRL PACKAGE (TOP VIEW) VCC 5 OE 1 A 2 GND 3 5 VCC 4 Y Y 4 Y 4 See mechanical drawings for dimensions. description/ordering information The SN74AHCT1G125 is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, true data is passed from the A input to the Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION SOT (SOT-23) − DBV −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA SOT (SC-70) − DCK SOT (SOT-553) − DRL Reel of 3000 SN74AHCT1G125DBVR Reel of 250 SN74AHCT1G125DBVT Reel of 3000 SN74AHCT1G125DCKR Reel of 250 SN74AHCT1G125DCKT Reel of 4000 SN74AHCT1G125DRLR TOP-SIDE MARKING‡ B25_ BM_ BM_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) OE A 1 2 4 Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated    !" # $%&" !#  '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
 
  
    
  SCLS378L − AUGUST 1997 − REVISED JUNE 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage VO IOH Output voltage IOL ∆t/∆v MIN MAX 4.5 5.5 High-level input voltage 2 UNIT V V 0.8 V 0 5.5 V 0 V High-level output current VCC −8 Low-level output current 8 mA 20 ns/V Input transition rise or fall rate mA TA Operating free-air temperature −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TA = 25°C TYP MAX MIN UNIT VOH IOH = −50 mA IOH = −8 mA 4.5 V VOL IOL = 50 mA IOL = 8 mA 4.5 V II IOZ VI = 5.5 V or GND VO = VCC or GND ICC VI = VCC or GND, IO = 0 5.5 V 1 10 mA ∆ICC‡ One input at 3.4 V, Other input at VCC or GND 5.5 V 1.35 1.5 mA Ci VI = VCC or GND VO = VCC or GND 10 10 pF Co 4.4 4.5 4.4 3.94 POST OFFICE BOX 655303 V 3.8 0.1 0.1 0.36 0.44 V 0 V to 5.5 V ±0.1 ±1 mA 5.5 V ±0.25 ±2.5 mA 5V 4 5V 10 ‡ This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. 2 MAX • DALLAS, TEXAS 75265 pF 
 
  
    
  SCLS378L − AUGUST 1997 − REVISED JUNE 2005 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25°C TYP MAX MIN MAX 3.8 5.5 1 6.5 3.8 5.5 1 6.5 3.6 5.1 1 6 3.6 5.1 1 6 4.6 6.8 1 8 4.6 6.8 1 8 5.3 7.5 1 8.5 5.3 7.5 1 8.5 5.1 7.1 1 8 5.1 7.1 1 8 6.1 8.8 1 10 6.1 8.8 1 10 UNIT ns ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 14 UNIT pF 3 
 
  
    
  SCLS378L − AUGUST 1997 − REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point RL = 1 kΩ From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL 1.5 V tPLZ ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPZH tPLH 50% VCC 3V Output Control VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 74AHCT1G125DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (B253 ~ B25G ~ B25J ~ B25L ~ B25S) 74AHCT1G125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (B253 ~ B25G ~ B25J ~ B25L ~ B25S) 74AHCT1G125DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (B253 ~ B25G ~ B25L ~ B25S) 74AHCT1G125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (B253 ~ B25G ~ B25L ~ B25S) 74AHCT1G125DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (BM3 ~ BMG ~ BMJ ~ BML ~ BMS) 74AHCT1G125DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (BM3 ~ BMG ~ BML ~ BMS) 74AHCT1G125DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (BM3 ~ BMG ~ BML ~ BMS) 74AHCT1G125DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (BMB ~ BMS) SN74AHCT1G125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (B253 ~ B25G ~ B25J ~ B25L ~ B25S) SN74AHCT1G125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (B253 ~ B25G ~ B25L ~ B25S) SN74AHCT1G125DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (BM3 ~ BMG ~ BMJ ~ BML ~ BMS) SN74AHCT1G125DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (BM3 ~ BMG ~ BML ~ BMS) SN74AHCT1G125DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (BMB ~ BMS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AHCT1G125 : • Automotive: SN74AHCT1G125-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74AHCT1G125DBVR SOT-23 DBV 5 3000 180.0 9.2 3.23 1.37 4.0 8.0 Q3 SN74AHCT1G125DBVR SOT-23 DBV 5 3000 178.0 9.2 SN74AHCT1G125DBVR SOT-23 DBV 5 3000 180.0 8.4 3.3 3.2 1.55 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 SN74AHCT1G125DBVT SOT-23 DBV 5 250 178.0 9.0 Q3 3.23 3.17 1.37 4.0 8.0 SN74AHCT1G125DBVT SOT-23 DBV 5 250 178.0 Q3 9.2 3.3 3.2 1.55 4.0 8.0 Q3 SN74AHCT1G125DCKR SC70 DCK 5 3000 SN74AHCT1G125DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 178.0 9.2 2.4 2.4 1.22 4.0 8.0 SN74AHCT1G125DCKT SC70 DCK 5 Q3 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74AHCT1G125DCKT SC70 DCK SN74AHCT1G125DCKT SC70 DCK 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 SN74AHCT1G125DRLR SOT Q3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74AHCT1G125DRLR SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 Pack Materials-Page 1 3.17 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 9-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHCT1G125DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0 SN74AHCT1G125DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74AHCT1G125DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74AHCT1G125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74AHCT1G125DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74AHCT1G125DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74AHCT1G125DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74AHCT1G125DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74AHCT1G125DCKT SC70 DCK 5 250 205.0 200.0 33.0 SN74AHCT1G125DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74AHCT1G125DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74AHCT1G125DRLR SOT DRL 5 4000 184.0 184.0 19.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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