SN74AHCT245DWRG4

Sample & Buy Product Folder Technical Documents Support & Community Tools & Software SN54AHCT245, SN74AHCT245 SCLS233P – OCTOBER 1995 – REVISED JULY 2014 SNx4AHCT245 Octal Bus Transceivers With 3-State Outputs 1 Features 3 Description • • The SNx4AHCT245 octal bus transceivers are designed for asynchronous two-way communication between data buses. These parts operate from 4.5 V to 5.5 V. 1 • • Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. Device Information(1) PART NUMBER SNx4AHCT245 PACKAGE BODY SIZE (NOM) PDIP (20) 25.40 x 6.35 mm SOP (20) 12.60 x 5.30 mm SSOP (20) 7.50 x 5.30 mm TVSOP (20) 5.00 x 4.40 mm SOIC (20) 12.80 x 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • • • Servers PCs and Notebooks Network Switches Wearable Health and Fitness Devices Telecom Infrastructures Electronic Points of Sale 4 Simplified Schematic 1 DIR 19 OE A1 2 18 B1 To Seven Other Channels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54AHCT245, SN74AHCT245 SCLS233P – OCTOBER 1995 – REVISED JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 4 4 4 5 5 6 6 6 6 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics......................................... Noise Characteristics ................................................ Operating Characteristics ........................................ Typical Characteristics .............................................. Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 9.1 9.2 9.3 9.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 8 8 8 8 10 Application and Implementation.......................... 9 10.1 Application Information............................................ 9 10.2 Typical Application .................................................. 9 11 Power Supply Recommendations ..................... 10 12 Layout................................................................... 10 12.1 Layout Guidelines ................................................. 10 12.2 Layout Example .................................................... 10 13 Device and Documentation Support ................. 11 13.1 13.2 13.3 13.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 11 11 11 11 14 Mechanical, Packaging, and Orderable Information ........................................................... 11 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision O (August 2013) to Revision P Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Added Military Disclaimer to Features list. ............................................................................................................................ 1 • Added Applications. ................................................................................................................................................................ 1 • Added Pin Functions table. .................................................................................................................................................... 3 • Added Handling Ratings table. ............................................................................................................................................... 4 • Added Thermal Information table. .......................................................................................................................................... 5 • Added Typical Characteristics. ............................................................................................................................................... 6 • Added Detailed Description section........................................................................................................................................ 8 • Added Application and Implementation section...................................................................................................................... 9 Changes from Revision N (March 2005) to Revision O Page • Removed Ordering Information table. .................................................................................................................................... 1 • Extended operating temperature range to 125°C................................................................................................................... 4 2 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 SN54AHCT245, SN74AHCT245 www.ti.com SCLS233P – OCTOBER 1995 – REVISED JULY 2014 6 Pin Configuration and Functions 19 3 18 4 17 5 6 16 15 7 14 8 13 9 12 10 11 A1 A2 A3 A4 A5 A6 A7 A8 20 19 OE 18 B1 2 3 17 B2 16 B3 4 5 15 B4 14 B5 6 7 13 B6 12 B7 8 9 10 11 A3 A4 A5 A6 A7 OE 1 A2 A1 DIR VCC VCC VCC OE B1 B2 B3 B4 B5 B6 B7 B8 SN54AHCT245 . . . FK PACKAGE (TOP VIEW) 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 B1 B2 B3 B4 B5 A8 GND B8 B7 B6 2 20 B8 1 DIR DIR A1 A2 A3 A4 A5 A6 A7 A8 GND SN74AHCT245 . . . RGY PACKAGE (TOP VIEW) GND SN54AHCT245 . . . J OR W PACKAGE SN74AHCT245 . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) Pin Functions PIN NO. NAME I/O DESCRIPTION 1 DIR — Direction Pin 2 A1 I/O A1 Input/Output 3 A2 I/O A2 Input/Output 4 A3 I/O A3 Input/Output 5 A4 I/O A4 Input/Output 6 A5 I/O A5 Input/Output 7 A6 I/O A6 Input/Output 8 A7 I/O A7 Input/Output 9 A8 I/O A8 Input/Output 10 GND — Ground Pin 11 B8 I/O B8 Input/Output 12 B7 I/O B7 Input/Output 13 B6 I/O B6 Input/Output 14 B5 I/O B5 Input/Output 15 B4 I/O B4 Input/Output 16 B3 I/O B3 Input/Output 17 B2 I/O B2 Input/Output 18 B1 I/O B1 Input/Output 19 OE I 20 VCC — Output Enable Power Pin Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 Submit Documentation Feedback 3 SN54AHCT245, SN74AHCT245 SCLS233P – OCTOBER 1995 – REVISED JULY 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage range (2) VI Input voltage range VO Output voltage range (2) Control inputs IIK Input clamp current VI < 0 IOK Output clamp current IO Continuous output current MIN MAX –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 Control inputs (2) V –20 mA VO < 0 or VO > VCC ±20 mA VO = 0 to VCC ±25 mA ±75 mA Continuous current through VCC or GND (1) UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT °C –65 150 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) SN54AHCT245 SN74AHCT245 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level Input voltage VI Input voltage 0 5.5 VO Output voltage 0 VCC IOH High-level output current –8 –8 IOL Low-level output current 8 8 mA Δt/Δv Input Transition rise and fall rate 20 20 ns/V TA Operating free-air temperature 125 °C (1) 4 2 2 0.8 –55 125 V V 0.8 V 0 5.5 V 0 VCC V –40 mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 SN54AHCT245, SN74AHCT245 www.ti.com SCLS233P – OCTOBER 1995 – REVISED JULY 2014 7.4 Thermal Information SN74AHCT245 THERMAL METRIC (1) DB DGV DW N NS PW RGY UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 96.0 116.1 79.8 51.5 77.1 102.8 35.1 RθJC(top) Junction-to-case (top) thermal resistance 57.7 31.3 45.8 38.2 43.6 36.8 43.3 RθJB Junction-to-board thermal resistance 51.2 57.6 47.4 32.4 44.6 53.8 12.9 ψJT Junction-to-top characterization parameter 19.4 1.0 18.5 24.6 17.2 2.5 0.9 ψJB Junction-to-board characterization parameter 50.8 56.9 47.0 32.3 44.2 53.3 12.9 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a n/a 7.9 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –50 µA VOH 4.5 V IOH = –8 mA IOL = 50 µA VOL MIN TYP 4.4 4.5 MAX 3.94 4.5 V IOH = 8 mA SN54AHCT245 –55°C TO 125°C TA = 25°C MIN MAX SN74AHCT245 –40°C TO 85°C MIN MAX Recommended SN74AHCT245 –40°C TO 125°C MIN 4.4 4.4 4.4 3.8 3.8 3.7 UNIT MAX V 0.1 0.1 0.1 0.1 0.36 0.44 0.44 0.44 V II OE or DIR VI = 5.5 V or GND 0 to 5.5 V ±0.1 ±1 (1) ±1 ±1 µA IOZ A or B inputs (2) VO = VCC or GND 5.5 V ±.25 ±2.5 ±2.5 ±2.5 µA 5.5 V 4 40 40 40 µA 5.5 V 1.35 1.5 1.5 1.5 mA ICC ΔICC VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND (3) Ci OE or DIR VI = VCC or GND 5V 2.5 Cio A or B inputs VI = VCC or GND 5V 4 (1) (2) (3) 10 10 pF pF On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 Submit Documentation Feedback 5 SN54AHCT245, SN74AHCT245 SCLS233P – OCTOBER 1995 – REVISED JULY 2014 7.6 www.ti.com Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) LOAD CAPACITANCE B or A CL = 15 pF OE A or B CL = 15 pF OE A or B CL = 15 pF A or B B or A CL = 50 pF OE A or B CL = 50 pF OE A or B CL = 50 pF tsk(o) (1) (2) CL = 50 pF SN54AHCT245 –55°C TO 125°C TA = 25°C TYP MAX MIN MAX 7.7 (1) 1 (1) 10 (1) 1 8.5 1 10 4.5 (1) 7.7 (1) 1 (1) 10 (1) 1 8.5 1 10 (1) (1) (1) (1) 13.8 1 MAX 16 MIN MAX Recommended SN74AHCT245 –40°C TO 125°C 4.5 (1) 8.9 MIN SN74AHCT245 –40°C TO 85°C 1 15 1 16 8.9 (1) 13.8 (1) 1 (1) 16 (1) 1 15 1 16 9.2 (1) 14.4 (1) 1 (1) 16.5 (1) 1 15.5 1 16.5 9.2 (1) 14.4 (1) 1 (1) 16.5 (1) 1 15.5 1 16.5 5.3 8.7 1 11 1 9.5 1 11 5.3 8.7 1 11 1 9.5 1 11 9.7 14.8 1 17 1 16 1 17 9.7 14.8 1 17 1 16 1 17 10 15.4 1 17.5 1 16.5 1 17.5 10 15.4 1 17.5 1 16.5 1 17.5 1 (2) UNIT ns ns ns ns ns ns 1 ns On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. 7.7 Noise Characteristics VCC = 5 V, CL = 50 pF, TA = 25°C (1) SN74AHCT245 PARAMETER VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 7.8 MIN TYP MAX UNIT 4 V 2 V 0.8 V Characteristics are for surface-mount packages only. Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, f = 1 MHz TYP 13 UNIT pF 7.9 Typical Characteristics 7 6 TPD (ns) 5 4 3 2 1 TPD in ns 0 -100 -50 0 50 Temperature (qC) 100 150 D001 Figure 1. SN74AHCT245 TPD vs Temperature, 15 pF Load 6 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 SN54AHCT245, SN74AHCT245 www.ti.com SCLS233P – OCTOBER 1995 – REVISED JULY 2014 8 Parameter Measurement Information Test Point From Output Under Test RL = 1 kΩ From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPLZ tPZL ≈VCC 50% VCC VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 Submit Documentation Feedback 7 SN54AHCT245, SN74AHCT245 SCLS233P – OCTOBER 1995 – REVISED JULY 2014 www.ti.com 9 Detailed Description 9.1 Overview The SNx7ACHT245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The SNx4AHCT245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction– control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagram 1 DIR 19 OE 2 A1 18 B1 To Seven Other Channels Figure 3. Logic Diagram (Positive Logic) 9.3 Feature Description • • • VCC is optimized at 5 V Allows up voltage translation from 3.3 V to 5 V – Inputs Accept VIH levels of 2 V Slow edge rates minimize output ringing 9.4 Device Functional Modes Table 1. Function Table (Each Transceiver) INPUTS OE 8 Submit Documentation Feedback DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 SN54AHCT245, SN74AHCT245 www.ti.com SCLS233P – OCTOBER 1995 – REVISED JULY 2014 10 Application and Implementation 10.1 Application Information The SN74AHCT245 is a low drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8 V VIL and 2 V VIH. This feature makes it ideal for translating up from 3.3 V to 5 V. The figure below shows this type of translation. 10.2 Typical Application Regulated 5 V OE VCC DIR A1 B1 5 V LEDs, Relays, 3.3 V µC or other system boards A8 B8 GND Figure 4. Typical Application Diagram 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure • Recommended input conditions – Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table. – Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC • Recommend output conditions – Load currents should not exceed 25 mA per output and 50 mA total for the part – Outputs should not be pulled above VCC Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 Submit Documentation Feedback 9 SN54AHCT245, SN74AHCT245 SCLS233P – OCTOBER 1995 – REVISED JULY 2014 www.ti.com Typical Application (continued) 10.2.3 Application Curves Output Input Figure 5. Typical Application Curve 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple-bit logic devices, inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled. 12.2 Layout Example Vcc Unused Input Input Output Output Unused Input Input Figure 6. Layout Diagram 10 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 SN54AHCT245, SN74AHCT245 www.ti.com SCLS233P – OCTOBER 1995 – REVISED JULY 2014 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54AHCT245 Click here Click here Click here Click here Click here SN74AHCT245 Click here Click here Click here Click here Click here 13.2 Trademarks All trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT245 SN74AHCT245 Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9681901Q2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629681901Q2A SNJ54AHCT 245FK 5962-9681901QRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9681901QR A SNJ54AHCT245J 5962-9681901QSA ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9681901QS A SNJ54AHCT245W SN74AHCT245DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245DBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245DGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT245 Samples SN74AHCT245DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT245 Samples SN74AHCT245N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT245N Samples SN74AHCT245NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT245 Samples SN74AHCT245PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245PWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245PWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245PWRG3 ACTIVE TSSOP PW 20 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245PWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB245 Samples SN74AHCT245RGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HB245 Samples Addendum-Page 1 Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Jun-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SNJ54AHCT245FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629681901Q2A SNJ54AHCT 245FK SNJ54AHCT245J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9681901QR A SNJ54AHCT245J SNJ54AHCT245W ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9681901QS A SNJ54AHCT245W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of