SN74AHCT594DBR

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN74AHCT594 SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 SN74AHCT594 8-Bit Shift Registers With Output Registers 1 Features 2 Applications • • • • • • • 1 • • • • Inputs Are TTL-Voltage Compatible 8-Bit Serial-In, Parallel-Out Shift Registers With Storage Independent Direct Overriding Clears on Shift and Storage Registers Independent Clocks for Both Shift and Storage Registers Latch-Up Performance Exceeds 100 mA Per JESD, 78 Class II ESD Protection Exceeds JESD 22 – 3500-V Human-Body Model – 200-V Machine Model – 2000-V Charged-Device Model Network Switches Power Infrastructure PCs, Notebooks Health and Fitness, Wearables Tests and Measurements 3 Description The SN74AHCT594 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Device Information(1) PART NUMBER SN74AHCT594 PACKAGE BODY SIZE (NOM) PDIP (16) 19.30 mm × 6.35 mm SSOP (16) 6.50 mm × 5.30 mm TSSOP (16) 5.00 mm × 4.40 mm SOP (16) 10.20 mm × 5.30 mm SOIC (16) 9.00 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AHCT594 SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 1 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings ............................................................ 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Electrical Characteristics........................................... 5 Timing Requirements, VCC = 5 V ± 0.5 V.................. 5 Switching Characteristics, VCC = 5 V ± 0.5 V............ 6 Noise Characteristics ................................................ 6 Operating Characteristics.......................................... 6 Typical Characteristics ............................................ 6 Parameter Measurement Information .................. 7 9 Detailed Description .............................................. 8 9.1 9.2 9.3 9.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 8 8 9 9 10 Application and Implementation........................ 10 10.1 Application Information.......................................... 10 10.2 Typical Application ............................................... 10 11 Power Supply Recommendations ..................... 11 12 Layout................................................................... 12 12.1 Layout Guidelines ................................................. 12 12.2 Layout Example .................................................... 12 13 Device and Documentation Support ................. 12 13.1 13.2 13.3 13.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 12 12 12 12 14 Mechanical, Packaging, and Orderable Information ........................................................... 12 5 Revision History Changes from Revision H (June 1998) to Revision I Page • Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 SN74AHCT594 www.ti.com SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 6 Pin Configuration and Functions Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 QB O Output B 2 QC O Output C 3 QD O Output D 4 QE O Output E 5 QF O Output F 6 QG O Output G 7 QH O Output H 8 GND — Ground Pin 9 QH' I QH inverted 10 SRCLR I Serial Clear 11 SRCLK I Serial Clock 12 RCLK I Storage Clock 13 RCLR I Storage Clear 14 SER I Serial Input 15 QA O Output A 16 VCC — Power pin Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 3 SN74AHCT594 SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 7 UNIT V (2) –0.5 7 V –0.5 VCC + 0.5 VI Input voltage range VO Output voltage range (2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±75 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) Storage Temperature Range –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 3500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 2000 Machine Model (MM) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) SN74AHCT594 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise and fall time TA Operating free-air temperature (1) 4 MIN MAX 4.5 5.5 UNIT V 2 V 0.8 V 0 5.5 V 0 VCC –8 –40 V mA 8 mA 20 ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, (SCBA004). Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 SN74AHCT594 www.ti.com SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 7.4 Thermal Information SN74AHCT594 THERMAL METRIC (1) D DB N NS PW UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 80.2 97.5 47.5 79.1 105.7 RθJC(top) Junction-to-case (top) thermal resistance 39.1 47.7 34.9 35.4 40.4 RθJB Junction-to-board thermal resistance 27.7 48.1 27.5 39.9 50.7 ψJT Junction-to-top characterization parameter 9.9 9.8 19.8 5.4 3.7 ψJB Junction-to-board characterization parameter 37.4 47.6 27.4 39.5 50.1 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II ICC ΔICC (2) Ci (1) (2) TEST CONDITIONS IOH = –50 µA VCC 4.5 V IOH = –8 mA IOL = 50 µA TA = 25°C MIN TYP 4.4 4.5 –40°C to 85°C MAX 3.94 4.5V IOL = 8 mA MIN –40°C to 125°C MAX MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.1 0.36 0.44 0.44 V VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 (1) ±1 (1) µA VI = VCC or GND, IO = 0 5.5 V 2 20 20 µA One input at 3.5 V, Other inputs at VCC or GND 5.5 V 2 2.2 2.2 mA 10 10 10 pF VI = VCC or GND 5V 2 On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. 7.6 Timing Requirements, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) TA = 25°C PARAMETER tw tsu th (1) Pulse duration Setup time Hold time MIN RCLK or SRCLK high or low –40°C to 85°C MAX MIN MAX –40°C to 125°C MIN 5 5.5 6.5 RCLR or SRCLR low 5.2 5.5 6 SER before SRCLK↑ 3 3 3.5 SRCLK↑ before RCLK↑ (1) 5 5 5.5 SRCLR low before RCLK↑ 5 5 5.5 SRCLR high (inactive) before SRCLK↑ 2.9 3.3 4 RCLR high (inactive) before RCLK↑ 3.4 3.8 4.5 2 2 2.5 SER after SRCLK↑ MAX UNIT ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 5 SN74AHCT594 SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 www.ti.com 7.7 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE fmax tPLH –40°C to 85°C MAX CL = 15 pF 135 (1) 170 (1) 115 115 CL = 50 pF 120 140 95 95 MAX MIN MAX 1 6.5 1 7.5 3.7 (1) 6.5 (1) 1 6.9 1 7.8 3.7 (1) 6.8 (1) 1 7.2 1 8 4.1 (1) 7.2 (1) 1 7.6 1 8.5 6.2 UNIT MHz (1) 3.3 (1) MIN –40°C to 125°C TYP RCLK QA – QH CL = 15 pF SRCLK QH' CL = 15 pF tPHL RCLR QA – QH CL = 15 pF 4.5 (1) 7.6 (1) 1 8.2 1 9.5 tPHL SRCLR QH' CL = 15 pF 4.1 (1) 7.1 (1) 1 7.6 1 8.5 RCLK QA – QH CL = 50 pF 4.9 7.8 1 8.3 1 9.5 5.8 8.9 1 9.7 1 10.5 SRCLK QH' CL = 50 pF 5.5 8.6 1 9.7 1 10 6 9.2 1 10.1 1 11 tPHL RCLR QA – QH CL = 50 pF 6.6 10 1 10.7 1 11.5 ns tPHL SRCLR QH' CL = 50 pF 6 9.2 1 10.1 1 11 ns tPHL tPLH tPHL tPLH tPHL tPLH tPHL (1) TA = 25°C MIN ns ns ns ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. 7.8 Noise Characteristics (1) VCC = 5 V, CL = 50 pF, TA = 25°C SN74AHCT594 PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 1 V VOL(V) Quiet output, minimum dynamic VOL –0.6 V VOH(V) Quiet output, minimum dynamic VOH 3.8 V VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 2 V 0.8 V TYP UNIT 112 pF Characteristics are for surface-mount packages only. 7.9 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, f = 1 MHz 7.10 Typical Characteristics 6 5 TPD (ns) 4 3 2 1 TPD in ns 0 -100 -50 0 50 Temperature (qC) 100 150 D001 Figure 1. TPD vs Temperature 6 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 SN74AHCT594 www.ti.com SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 8 Parameter Measurement Information A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 7 SN74AHCT594 SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 www.ti.com 9 Detailed Description 9.1 Overview The ’AHCT594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (SRCLR, RCLR) inputs are provided on both the shift and storage registers. A serial (QH′) output is provided for cascading purposes. Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one count pulse ahead of the storage register. 9.2 Functional Block Diagram 8 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 SN74AHCT594 www.ti.com SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 9.3 Feature Description • • • • VCC is optimized at 5 V Allow Up voltage translation from 3.3 V to 5 V – Inputs accept VIH levels of 2 V Slow edge rates minimize output ringing Inputs are TTL-Voltage compatible 9.4 Device Functional Modes Table 1. Function Table INPUTS FUNCTION SER SRCLK SRCLR RCLK RCLR X X L X X Shift register is cleared. L ↑ H X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. L ↓ H X X Shift-register state is not changed. X X X X L Storage register is cleared. X X X ↑ H Shift-register data is stored in the storage register. X X X ↓ H Storage-register state is not changed. Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 9 SN74AHCT594 SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information SN74AHCT594 is a low drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8 V VIL and 2 V VIH. This feature makes it Ideal for translating up from 3.3 V to 5 V. Figure 4 shows this type of translation. 10.2 Typical Application Digital signals from control unit +5 V Power QB QC QD QE QF QG QH GND + LED LED Resistor 500 Ω + LED + Resistor 500 Ω 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 LED Resistor 500 Ω + LED Resistor 500 Ω VCC QA SER RCLR RCLK SRCLK SRCLR QH’ + LED Resistor 500 Ω + + LED Resistor 500 Ω LED Resistor 500 Ω + LED Resistor 500 Ω Figure 3. Application Schematic 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 10 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 SN74AHCT594 www.ti.com SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 Typical Application (continued) 10.2.2 Detailed Design Procedure 1. Recommended Input conditions – Rise time and fall time specs see (Δt/ΔV) in Recommended Operating Conditions table. – Specified High and low levels. See (VIH and VIL) in Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid Vcc 2. Recommend output conditions – Load currents should not exceed 25 mA per output and 75 mA total for the part – Outputs should not be pulled above VCC Voltage 10.2.3 Application Curves Time Figure 4. Typical Application Curve 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 11 SN74AHCT594 SCLS417I – JUNE 1998 – REVISED DECEMBER 2014 www.ti.com 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 5 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 12.2 Layout Example Vcc Input Unused Input Output Output Unused Input Input Figure 5. Layout Diagram 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN74AHCT594 Click here Click here Click here Click here Click here 13.2 Trademarks All trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated Product Folder Links: SN74AHCT594 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AHCT594D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT594 SN74AHCT594DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB594 SN74AHCT594DG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT594 SN74AHCT594DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT594 SN74AHCT594N ACTIVE PDIP N 16 25 RoHS & Non-Green NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT594N SN74AHCT594NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT594 SN74AHCT594PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB594 SN74AHCT594PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB594 SN74AHCT594PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB594 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of