SN74AHCT74MDREP

SN74AHCT74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS495– JUNE 2003 D D D D D D D D D D OR PW PACKAGE (TOP VIEW) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. description/ordering information The SN74AHCT74 is a dual positive-edge-triggered D-type flip-flop. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION –55°C 55°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA SOIC – D Tape and reel SN74AHCT74MDREP TSSOP – PW Tape and reel SN74AHCT74MPWREP TOP-SIDE MARKING AHCT74MEP AHT74EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AHCT74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS495– JUNE 2003 FUNCTION TABLE OUTPUTS INPUTS PRE CLR CLK D Q L H X X H Q L H L X X H H† L L X X L H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic symbol‡ 1PRE 4 1CLK 1CLR 2PRE 1D 1 6 1Q R 10 9 11 2CLK 1Q C1 2 1D 5 S 3 2Q 12 2D 8 2CLR 13 2Q ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AHCT74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS495– JUNE 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage VO IOH Output voltage IOL ∆t/∆v Low-level output current MIN MAX 4.5 5.5 High-level input voltage 2 UNIT V V 0.8 V 0 5.5 V 0 VCC –8 High-level output current Input transition rise or fall rate V mA 8 mA 20 ns/V TA Operating free-air temperature –55 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C MIN TYP MAX MIN MAX UNIT VOH IOH = –50 mA IOH = –8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA 45V 4.5 II ICC VI = 5.5 V or GND VI = VCC or GND, ±0.1 ±1 mA IO = 0 5.5 V 2 20 mA ∆ICC‡ One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 mA 0 V to 5.5 V Ci 4.4 4.5 4.4 3.94 0.1 0.1 0.36 0.44 VI = VCC or GND 5V 2 10 ‡ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 3.8 V pF 3 SN74AHCT74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS495– JUNE 2003 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN PRE or CLR low 5 5 CLK 5 5 Data 5 5 3.5 3.5 0 0 PRE or CLR inactive MAX UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX LOAD CAPACITANCE MIN CL = 15 pF 100 160 80 CL = 50 pF 80 140 65 tPLH tPHL PRE or CLR Q or Q CL = 15 pF tPLH tPHL CLK Q or Q CL = 15 pF tPLH tPHL PRE or CLR Q or Q CL = 50 pF tPLH tPHL CLK Q or Q CL = 50 pF MIN MAX UNIT MHz 7.6 10.4 1 12 7.6 10.4 1 12 5.8 7.8 1 9 5.8 7.8 1 9 8.1 11.4 1 13 8.1 11.4 1 13 6.3 8.8 1 10 6.3 8.8 1 10 MIN MAX ns ns ns ns noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) PARAMETER UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4 V High-level dynamic input voltage 2 V Quiet output, minimum dynamic VOL VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. 0.8 V –0.8 V 0.8 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 32 pF SN74AHCT74-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCLS495– JUNE 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test tw Test Point 3V CL (see Note A) 1.5 V Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION LOAD CIRCUIT 3V Input (see Note B) 1.5 V 1.5 V 0V tPLH 3V Timing Input (see Note B) 1.5 V In-Phase Output tPHL 50% VCC 0V th tsu tPHL 3V Data Input 1.5 V 1.5 V 0V Out-of-Phase Output VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr C. The outputs are measured one at a time with one input transition per measurement. + 3 ns, tf + 3 ns. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AHCT74MDREP ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 AHCT74MEP SN74AHCT74MPWREP ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 AHT74EP V62/03659-01XE ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 AHT74EP V62/03659-01YE ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 AHCT74MEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of