SN74AHCT74PWR

SN54AHCT74 SN74AHCT74 www.ti.com SCLS263O – OCTOBER 1995 – REVISED JUNE 2013 QUADRUPLE 2-INPUT POSITIVE-NAND GATES Check for Samples: SN54AHCT74, SN74AHCT74 Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q 1D 1CLK 1PRE 1Q 1Q 14 1D 1 SN54AHCT74 . . . FK PACKAGE (TOP VIEW) 2 13 2CLR 3 12 2D 4 11 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q 2CLK 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q 14 2 VCC 1 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1CLR SN74AHCT74 . . . RGY PACKAGE (TOP VIEW) SN54AHCT74 . . . J or W PACKAGE SN74AHCT74 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) GND • • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2CLR • 1CLR NC VCC FEATURES 1 NC − No internal connection DESCRIPTION The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. FUNCTION TABLE (EACH FLIP-FLOP) INPUTS (1) OUTPUT PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H (1) H (1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 This configuration is non-stable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995–2013, Texas Instruments Incorporated SN54AHCT74 SN74AHCT74 SCLS263O – OCTOBER 1995 – REVISED JUNE 2013 www.ti.com LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Supply voltage range, VCC –0.5 to 7 V Input voltage range, VI (2) –0.5 to 7 V Output voltage range, VO (2) –0.5 to VCC + 0.5 V Input clamp current, IIK (VI < 0) –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA Continuous output current, IO (VO = 0 to VCC) ±25 mA Continuous current through VCC or GND ±50 mA D package Package thermal impedance, θJA (3) 86 DB package (3) 96 DGV package (3) 127 N package (3) 80 NS package (3) 76 PW package (3) 113 RGY package (4) 47 Storage temperature range, Tstg (1) (2) (3) (4) 2 –65 to 150 °C/W °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: SN54AHCT74 SN74AHCT74 SN54AHCT74 SN74AHCT74 www.ti.com SCLS263O – OCTOBER 1995 – REVISED JUNE 2013 RECOMMENDED OPERATING CONDITIONS (1) SN54AHCT74 SN74AHCT74 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V IOH High-level output current –8 –8 IOL Low-level output current 8 8 mA Δt/Δv Input Transition rise or fall rate 20 20 ns/V TA Operating free-air temperature 125 °C (1) 2 V 2 V 0.8 –55 125 –40 mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II ICC ΔICC Ci (1) TEST CONDITIONS IOH = –50 µA 4.5 V IOH = –8 mA IOL = 50 µA MIN TYP 4.4 4.5 VI = 5.5 V or GND IO = 0 One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND TA = –40°C TO 85°C SN54AHCT74 SN74AHCT74 MAX MIN 3.94 MAX MIN TA = –40°C TO 125°C Recommended UNIT SN74AHCT74 MAX MIN 4.4 4.4 4.4 3.8 3.8 3.8 MAX V 0.1 0.1 0.1 0.1 0.36 0.44 0.44 0.44 ±0.1 ±1 (1) ±1 ±1 µA 5.5 V 2 20 20 20 µA 5.5 V 1.35 1.5 1.5 1.5 mA 4.5 V IOH = 8 mA VI = VCC or GND, TA = 25°C VCC TA = –55°C TO 125°C 0 V to 5.5 V 5V 2 10 10 V pF On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. TIMING REQUIREMENTS over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C PARAMETER TYP tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MAX TA = –40°C TO 125°C TA = –55°C TO 125°C TA = –40°C TO 85°C SN54AHCT74 SN54AHCT74 SN54AHCT74 MIN MIN MIN MAX MAX Recommended MAX PRE or CLR low 5 5 5 5 CLK 5 5 5 5 Data 5 5 5 5 3.5 3.5 3.5 3.5 0 0 0 0 PRE or CLR inactive Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: SN54AHCT74 SN74AHCT74 UNIT Submit Documentation Feedback ns ns ns 3 SN54AHCT74 SN74AHCT74 SCLS263O – OCTOBER 1995 – REVISED JUNE 2013 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL (1) TA = 25°C LOAD CAPACITANCE TA = –40°C TO 85°C SN54AHCT74 SN54AHCT74 SN54AHCT74 MIN MIN MIN MIN TYP 100 (1) 160 (1) 90 80 80 CL = 50pF 80 140 65 65 65 Q or Q CL = 15 pF CLK Q or Q CL = 15 pF PRE or CLR Q or Q CL = 50 pF CLK Q or Q CL = 50 pF MAX MAX Recommended CL = 15 pF PRE or CLR MAX TA = –40°C TO 125°C TA = –55°C TO 125°C UNIT MAX ns 7.6 (1) 10.4 (1) 1 (1) 12 (1) 1 12 1 12 7.6 (1) 10.4 (1) 1 (1) 12 (1) 1 12 1 12 5.8 (1) 7.8 (1) 1 (1) 9 (1) 1 9 1 9.0 5.8 (1) 7.8 (1) 1 (1) 9 (1) 1 9 1 9.0 8.1 11.4 1 13 1 13 1 13 8.1 11.4 1 13 1 13 1 13 6.3 8.8 1 10 1 10 1 10 6.3 8.8 1 10 1 10 1 10 ns ns ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. NOISE CHARACTERISTICS VCC = 5 V, CL = 50 pF, TA = 25°C (1) SN54AHCT74 PARAMETER MIN UNIT MAX VOL(P) Quiet output, maximum dynamic VOL 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.8 V VOH(V) Quiet output, minimum dynamic VOH 4 V VIH(D) High-level dynamic input voltage 2 V VIL(D) Low-level dynamic input voltage (1) 0.8 V Characteristics are for surface-mount packages only. OPERATING CHARACTERISTICS VCC = 5 V, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance Submit Documentation Feedback TEST CONDITIONS No load, f = 1 MHz TYP 32 UNIT pF Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: SN54AHCT74 SN74AHCT74 SN54AHCT74 SN74AHCT74 www.ti.com SCLS263O – OCTOBER 1995 – REVISED JUNE 2013 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test RL = 1 kΩ From Output Under Test S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH In-Phase Output 50% VCC 50% VCC VOL tPHL Out-of-Phase Output Output Waveform 1 S1 at VCC (see Note B) 1.5 V VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control VOL + 0.3 V VOL tPHZ Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: SN54AHCT74 SN74AHCT74 Submit Documentation Feedback 5 SN54AHCT74 SN74AHCT74 SCLS263O – OCTOBER 1995 – REVISED JUNE 2013 www.ti.com REVISION HISTORY Changes from Revision N (July 2003) to Revision O Page • Changed document format from Quicksilver to DocZone. .................................................................................................... 1 • Extended operating temperature range to 125°C ................................................................................................................. 3 6 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: SN54AHCT74 SN74AHCT74 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9686101Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629686101Q2A SNJ54AHCT 74FK 5962-9686101QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9686101QC A SNJ54AHCT74J 5962-9686101QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9686101QD A SNJ54AHCT74W SN74AHCT74D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT74 SN74AHCT74DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HB74 SN74AHCT74DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HB74 SN74AHCT74DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT74 SN74AHCT74N ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT74N SN74AHCT74NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT74 SN74AHCT74PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HB74 SN74AHCT74PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HB74 SN74AHCT74PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HB74 SN74AHCT74PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HB74 SN74AHCT74RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HB74 SNJ54AHCT74FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629686101Q2A SNJ54AHCT Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2018 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 74FK SNJ54AHCT74J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9686101QC A SNJ54AHCT74J SNJ54AHCT74W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9686101QD A SNJ54AHCT74W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of