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SN74AHCT86RGYRG4

SN74AHCT86RGYRG4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VFQFN14

  • 描述:

    IC GATE XOR 4CH 2-INP 14VQFN

  • 数据手册
  • 价格&库存
SN74AHCT86RGYRG4 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN54AHCT86, SN74AHCT86 SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 SNx4AHCT86 Quadruple 2-Input Exclusive-OR Gates 1 Features 3 Description • • The SNx4AHCT86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function Y = A × B or Y = AB + AB in positive logic. 1 • • Inputs are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 On Products Compliant to MIL-PRF-38535, All Parameters are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) Device Information(1) PART NUMBER SNx4AHCT574 BODY SIZE (NOM) TVSOP (14) 3.60 mm × 4.40 mm SOIC (14) 8.65 mm × 3.91 mm SOP (14) 10.30 mm × 5.30 mm SSOP (14) 6.20 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • • • PACKAGE Server PCs and Notebooks Network Switches Wearable Health and Fitness Devices Telecom Infrastructures Electronic Points of Sale 4 Simplified Schematic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These are five equivalent exclusive-OR symbols valid for an SN74AHCT86 gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT = The output is active (low) if all inputs stand at the same logic level (that is, A = B). EVEN-PARITY ELEMENT 2k The output is active (low) if an even number of inputs (that is, 0 or 2) are active. ODD-PARITY ELEMENT 2k + 1 The output is active (high) if an odd number of inputs (that is, only 1 of the 2) are active. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54AHCT86, SN74AHCT86 SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 4 4 4 5 5 5 6 6 6 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Noise Characteristics ................................................ Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 9.1 9.2 9.3 9.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 8 8 8 8 10 Application and Implementation.......................... 9 10.1 Application Information............................................ 9 10.2 Typical Application ................................................. 9 11 Power Supply Recommendations ..................... 10 12 Layout................................................................... 10 12.1 Layout Guidelines ................................................. 10 12.2 Layout Example .................................................... 10 13 Device and Documentation Support ................. 11 13.1 13.2 13.3 13.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 11 11 11 11 14 Mechanical, Packaging, and Orderable Information ........................................................... 11 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision M (July 2003) to Revision N Page • Updated document to new TI data sheet format. ................................................................................................................... 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Added Military Disclaimer to Features list. ............................................................................................................................. 1 • Added Applications. ................................................................................................................................................................ 1 • Added Pin Functions table...................................................................................................................................................... 3 • Added Handling Ratings table. ............................................................................................................................................... 4 • Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 4 • Added Thermal Information table. .......................................................................................................................................... 5 • Added –40°C to 125°C for SN74AHCT86 in the Electrical Characteristics table................................................................... 5 • Added –40°C to 125°C for SN74AHCT86 in the Switching Characteristics table.................................................................. 5 • Added Typical Characteristics. ............................................................................................................................................... 6 • Added Detailed Description section........................................................................................................................................ 8 • Added Application and Implementation section...................................................................................................................... 9 • Added Power Supply Recommendations and Layout sections............................................................................................ 10 2 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 SN54AHCT86, SN74AHCT86 www.ti.com SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 6 Pin Configuration and Functions SN54AHCT86 . . . J OR W PACKAGE SN74AHCT86 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) 13 3 12 4 11 5 10 6 9 7 8 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B VCC 1 1Y NC 2A NC 2B 13 4B 2 3 12 4A 4 4Y 10 3B 9 3A 11 5 6 7 8 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 2 VCC 4B 4A 4Y 3B 3A 3Y 3Y 14 1A 1 GND 1A 1B 1Y 2A 2B 2Y GND SN54AHCT86 . . . FK PACKAGE (TOP VIEW) SN74AHCT86 . . . RGY PACKAGE (TOP VIEW) NC − No internal connection Pin Functions PIN SN74AHCT86 NAME SN54AHCT86 I/O DESCRIPTION D, DB, DGV, N, NS, PW RGY J, W FK 1A 1 1 1 2 I 1A Input 1B 2 2 2 3 I 1B Input 1Y 3 3 3 4 O 1Y Output 2A 4 4 4 6 I 2A Input 2B 5 5 5 8 I 2B Input 2Y 6 6 6 9 O 2Y Output 3Y 8 8 8 12 O 3Y Output 3A 9 9 9 13 I 3A Input 3B 10 10 10 14 I 3B Input 4Y 11 11 11 16 O 4Y Output 4A 12 12 12 18 I 4A Input 4B 13 13 13 19 I 4B Input GND 7 7 7 10 — Ground Pin — No Connection — Power Pin 1 5 NC — — — 7 11 15 17 VCC 14 14 14 20 Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 Submit Documentation Feedback 3 SN54AHCT86, SN74AHCT86 SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 7 UNIT V (2) –0.5 7 V –0.5 VCC + 0.5 VI Input voltage range VO Output voltage range (2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA Continuous current through VCC or GND (1) (2) V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT °C –65 150 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) SN54AHCT86 SN74AHCT86 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 0 5.5 VO Output voltage 0 VCC IOH High-level output current –8 –8 IOL Low-level output current 8 8 mA ∆t/∆v Input transition rise or fall rate 20 20 ns/V TA Operating free-air temperature 125 °C (1) 4 2 2 0.8 –55 V 125 V 0.8 V 0 5.5 V 0 VCC V –40 mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 SN54AHCT86, SN74AHCT86 www.ti.com SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 7.4 Thermal Information SN74AHCT86 THERMAL METRIC (1) D DB DGV N NS PW RGY UNIT 14 PINS RθJA Junction-to-ambient thermal resistance 97.5 109.5 133.3 59.7 92.2 125.1 59.0 RθJC(top) Junction-to-case (top) thermal resistance 58.7 62.1 55.6 47.3 49.8 53.7 72.5 RθJB Junction-to-board thermal resistance 51.8 56.9 66.3 39.5 51.0 66.9 35.0 ψJT Junction-to-top characterization parameter 22.6 22.6 7.8 32.4 15.7 7.6 3.9 ψJB Junction-to-board characterization parameter 51.6 56.3 56.6 39.4 50.6 66.3 35.1 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a n/a 15.4 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II ICC ΔICC (2) Ci (1) (2) TEST CONDITIONS TA = 25°C VCC IOH = −50 µA 4.5 V IOH = −8 mA IOL = 50 µA MIN TYP 4.4 4.5 IOL = 8 mA MAX 3.94 4.5 V –40°C to 85°C SN74AHCT86 SN54AHCT86 MIN MAX MIN –40°C to 125°C SN74AHCT86 MAX MIN 4.4 4.4 4.4 3.8 3.8 3.8 UNIT MAX V 0.1 0.1 0.1 0.1 0.36 0.44 0.44 0.44 V VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 (1) ±1 ±1 µA VI = VCC or GND, IO = 0 5.5 V 2 20 20 20 µA One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 1.5 mA VI = VCC or GND 5V 4 10 10 pF On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. 7.6 Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN tPLH A or B Y tPHL tPLH tPHL (1) A or B Y CL = 15 pF CL = 50 pF –55°C to 125°C SN54AHCT86 TA = 25°C LOAD CAPACITANCE –40°C to 85°C SN74AHCT86 –40°C to 125°C SN74AHCT86 UNIT TYP MAX MIN MAX MIN MAX MIN MAX 5 (1) 6.9 (1) 1 (1) 8 (1) 1 8 1 9 5 (1) 6.9 (1) 1 (1) 8 (1) 1 8 1 9 5.5 8.8 1 10 1 9 1 11 5.5 8.8 1 10 1 9 1 11 ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 Submit Documentation Feedback 5 SN54AHCT86, SN74AHCT86 SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 www.ti.com 7.7 Noise Characteristics VCC = 5 V, CL = 50 pF, TA = 25°C (1) SN74AHCT86 PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.4 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.4 –0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 4.4 V 2 V 0.8 V Characteristics are for surface-mount packages only. 7.8 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, f = 1 MHz TYP 18 UNIT pF 7.9 Typical Characteristics 7 6 TPD (ns) 5 4 3 2 1 TPD in ns 0 -100 -50 0 50 Temperature (qC) 100 150 D001 Figure 1. TPD vs Temperature 6 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 SN54AHCT86, SN74AHCT86 www.ti.com SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 8 Parameter Measurement Information VCC Test Point From Output Under Test RL = 1 kΩ From Output Under Test S1 Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control VOL + 0.3 V VOL tPHZ Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 Submit Documentation Feedback 7 SN54AHCT86, SN74AHCT86 SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 www.ti.com 9 Detailed Description 9.1 Overview The SNx4AHCT86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function Y = A × B or Y = AB + AB in positive logic. The inputs are TTL compatible allowing 3.3 V to 5 V translation. 9.2 Functional Block Diagram An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These are five equivalent exclusive-OR symbols valid for an SN74AHCT86 gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT = ODD-PARITY ELEMENT 2k The output is active (low) if all inputs stand at the same logic level (that is, A = B). 2k + 1 The output is active (low) if an even number of inputs (that is, 0 or 2) are active. The output is active (high) if an odd number of inputs (that is, only 1 of the 2) are active. Figure 3. Exclusive-OR Logic 9.3 Feature Description • • TTL inputs – Lowered switching threshold allows up translation 3.3 V to 5 V Slow edges reduce output ringing 9.4 Device Functional Modes Table 1. Function Table (Each Gate) INPUTS A 8 Submit Documentation Feedback B OUTPUT Y L L L L H H H L H H H L Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 SN54AHCT86, SN74AHCT86 www.ti.com SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 10 Application and Implementation 10.1 Application Information The SNx4AHCT86 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V VIL and 2-V VIH. This feature makes the device ideal for translating up from 3.3 V to 5 V. Figure 5 shows this type of translation. 10.2 Typical Application 3.3-V Bus Driver VCC 5 V Regulated 0.1 µF 5-V Accessory Figure 4. Typical Application Schematic 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads; therefore, routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended input conditions – Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table. – Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC 2. Recommend output conditions – Load currents should not exceed 25 mA per output and 75 mA total for the part – Outputs should not be pulled above VCC Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 Submit Documentation Feedback 9 SN54AHCT86, SN74AHCT86 SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 www.ti.com Typical Application (continued) 10.2.3 Application Curves Figure 5. Up Translation 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 6 are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the IOs so they cannot float when disabled. 12.2 Layout Example Vcc Unused Input Input Output Output Unused Input Input Figure 6. Layout Diagram 10 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 SN54AHCT86, SN74AHCT86 www.ti.com SCLS250N – OCTOBER 1995 – REVISED AUGUST 2014 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54AHCT86 Click here Click here Click here Click here Click here SN74AHCT86 Click here Click here Click here Click here Click here 13.2 Trademarks All trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHCT86 SN74AHCT86 Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9681701Q2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629681701Q2A SNJ54AHCT 86FK 5962-9681701QCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9681701QC A SNJ54AHCT86J SN74AHCT86D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT86 Samples SN74AHCT86DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB86 Samples SN74AHCT86DGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB86 Samples SN74AHCT86DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT86 Samples SN74AHCT86N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT86N Samples SN74AHCT86NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT86 Samples SN74AHCT86PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB86 Samples SN74AHCT86PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB86 Samples SN74AHCT86RGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HB86 Samples SN74AHCT86RGYRG4 ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HB86 Samples SNJ54AHCT86FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629681701Q2A SNJ54AHCT 86FK SNJ54AHCT86J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9681701QC A SNJ54AHCT86J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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