SDAS159D − APRIL 1982 − REVISED DECEMBER 1994
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•
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D OR N PACKAGE
(TOP VIEW)
AND-Gated ( Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
A
B
QA
QB
QC
QD
GND
description
1
14
2
13
3
12
4
11
5
10
6
9
7
VCC
QH
QG
QF
QE
CLR
CLK
8
This 8-bit parallel-out serial shift register features
AND-gated serial (A and B) inputs and an
asynchronous clear (CLR) input. The gated serial
inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which
determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,
provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition
of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
OUTPUTS†
INPUTS
CLR
CLK
A
B
QA
QB . . . QH
L
X
X
X
L
L
L
H
L
X
X
QA0
QB0
QH0
H
↑
H
H
H
QAn
QGn
H
↑
L
X
L
QAn
QGn
H
↑
X
L
L
QAn
QGn
† QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established.
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
↑ = transition from low to high level
QAn, QGn = the level of QA or QG before the most recent
↑ transition of the clock; indicates a 1-bit shift.
Copyright 1994, Texas Instruments Incorporated
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SDAS159D − APRIL 1982 − REVISED DECEMBER 1994
logic symbol†
SRG8
9
CLR
R
8
CLK
C1/
1
A
&
3
2
B
QA
1D
4
QB
5
QC
6
QD
10
QE
11
QF
12
QG
13
QH
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
CLR
Serial Inputs
CLK
2
9
8
1
A
B
2
R
1R
R
1R
C1
R
1R
C1
1S
R
1R
C1
1S
R
1R
C1
1S
C1
1S
3
4
5
6
QB
QC
QD
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R
1R
C1
1S
QA
•
R
1R
C1
1S
10
QE
R
1R
C1
1S
11
QF
1S
12
QG
13
QH
SDAS159D − APRIL 1982 − REVISED DECEMBER 1994
typical clear, shift, and clear sequences
Serial Inputs
CLR
A
B
CLK
QA
QB
Outputs
QC
QD
QE
QF
QG
QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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3
SDAS159D − APRIL 1982 − REVISED DECEMBER 1994
recommended operating conditions
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
fclock
High-level input voltage
MIN
NOM
MAX
4.5
5
5.5
2
UNIT
V
V
0.8
V
High-level output current
−0.4
mA
Low-level output current
8
mA
50
MHz
Clock frequency
CLK
10
CLR low
16
tw
Pulse duration
tsu
Setup time before CLK↑
th
TA
Hold time, data after CLK↑
2
Operating free-air temperature
0
Data
6
CLR inactive
8
ns
ns
ns
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = − 18 mA
IOH = − 0.4 mA
VOL
VCC = 4.5 V
IOL = 4 mA
IOL = 8 mA
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
TYP†
MAX
UNIT
−1.5
V
VCC − 2
V
0.25
0.4
0.35
0.5
0.1
−30
V
mA
20
µA
−0.1
mA
−112
mA
ICC
VCC = 5.5 V,
See Note 1
14
24
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: With 4.5 V applied to the serial input and all other inputs, except the CLK, grounded, ICC is measured after a clock transition from
0 to 4.5 V.
switching characteristics (see Figure 1)
PARAMETER
fmax
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
CLR
Any Q
Any Q
CLK
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX§
MIN TYP¶
MAX
50
75
6
15
20
4
9
16
5
11
17
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
¶ All typical values are at VCC = 5 V, TA = 25°C.
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UNIT
MHz
ns
ns
SDAS159D − APRIL 1982 − REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
From Output
Under Test
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
3.5 V
Input
tPHZ
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
VOL
0.3 V
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
1.3 V
1.3 V
[3.5 V
1.3 V
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
Out-of-Phase
Output
(see Note C)
0.3 V
[0 V
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74ALS164AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS164A
SN74ALS164ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS164A
SN74ALS164AN
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74ALS164AN
SN74ALS164ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS164A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of