SN74ALS166DBR

SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000 D D D D Synchronous Load Direct Overriding Clear Parallel-to-Serial Conversion Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages and Standard Plastic (N) DIP D, DB, OR N PACKAGE (TOP VIEW) SER A B C D CLK INH CLK GND description The SN74ALS166 parallel-load 8-bit shift register is compatible with most other TTL logic families. All inputs are buffered to lower the drive requirements. Input clamping diodes minimize switching transients and simplify system design. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC SH/LD H QH G F E CLR These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial data (SER) input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data (A–H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running and the register can be stopped on command with the clock input. CLK INH should be changed to the high level only when CLK is high. The buffered CLR overrides all other inputs, including CLK, and sets all flip-flops to zero. The SN74ALS166 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS PARALLEL INTERNAL OUTPUTS OUTPUT QH CLR SH/LD CLK INH CLK SER A...H QA L X X X X X L L L H X L L X X QA0 QB0 QH0 QB H L L ↑ X a...h a b h H H L ↑ H X H QAn QGn H H L ↑ L X L QAn QGn H X H ↑ X X QA0 QB0 QH0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000 logic symbol† CLR 9 R 15 M1 [Shift] M2 [Load] SH/LD CLK INH CLK SER A B C D E F G H SRG8 6 ≥1 7 1 C3/1 1, 3D 2 2, 3D 3 2, 3D 4 5 10 11 12 14 13 QH † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. logic diagram (positive logic) SER 1 SH/LD CLR B 2 C 3 D 4 E 5 F G H 10 11 12 14 R 1A C1 1S R 1A C1 1S R 1A C1 1S R 1A C1 1S 15 9 7 CLK CLK INH 6 2 A R 1A C1 1S R 1A C1 1S R 1A C1 1S POST OFFICE BOX 655303 R 1A C1 1S • DALLAS, TEXAS 75265 13 QH SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000 typical clear, shift, load, inhibit, and shift sequences CLK CLK INH CLR SER SH/LD Parallel Inputs A H B L C H D L E H F L G H H H QH Serial Shift Clear H Inhibit H L H L L H H Serial Shift Load absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA Low-level output current High-level input voltage MIN NOM MAX 4.5 5 5.5 2 High-level output current Operating free-air temperature 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V –0.4 mA 8 mA 70 °C 3 SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –0.4 mA VOL VCC = 4 4.5 5V IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V TYP† MAX UNIT –1.5 V VCC–2 V 0.25 0.4 0.35 0.5 0.1 –30 V mA 20 µA –0.1 mA –112 mA ICC VCC = 5.5 V, See Note 2 14 24 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 2: With 4.5 V applied to SER and all other inputs, except the clock, grounded, ICC is measured after a clock transition from 0 V to 4.5 V. timing requirements over recommended operating free-air temperature range (unless otherwise noted) MIN fclock tw tsu Clock frequency Pulse duration Setup time before CLK↑ ↑ CLR low 9 CLK high 10 CLK low 10 SH/LD 16 Data UNIT 45 MHz ns ns 7 CLR inactive th MAX 11 Hold time, data after CLK↑ 3 ns switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPHL CLR QH tPLH tPHL CLK QH PARAMETER fmax MAX 4 9 14 2 7 12 2 9 13 45 † All typical values are at VCC = 5 V, TA = 25°C. 4 TYP† MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz ns ns SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000 PARAMETER MEASUREMENT INFORMATION Test Point TEST TABLE FOR SYNCHRONOUS INPUTS From Output Under Test CL = 50 pF (see Note A) RL = 500 Ω DATA INPUT FOR TEST SH/LD OUTPUT TESTED (see Note B) H 0V QH at tn + 1 Serial input 4.5 V QH at tn + 1 LOAD CIRCUIT FOR OUTPUT UNDER TEST tw(clear) 3.5 V CLR (see Note C) CLK (see Note E) 1.3 V 1.3 V 0.3 V tn 1.3 V 1.3 V tn + 1 (see Note D) tn 1.3 V tn + 1 3.5 V 1.3 V 0.3 V tw(CLK) tsu th tsu 1.3 V 1.3 V th 3.5 Data Input (see Test Table) 1.3 V 1.3 V 0.3 V tPHL tPLH tPHL VOH Output QH VOL VOLTAGE WAVEFORMS NOTES: A. B. C. D. E. CL includes probe and jig capacitance. Propagation delay times (tPLH and tPHL) are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test. A clear pulse is applied prior to each test. tn = bit time before clocking transition, tn+1 = bit time after one clocking transition, and tn+8 = bit time after eight clocking transitions. The clock pulse has the following characteristics: tw(clock) ≤ 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics: tw(clear) ≤ 20 ns. F. All pulse generators have the following characteristics: ZO ≈ 50 Ω; tr = tf = 2 ns. Duty cycle = 50% when testing fmax. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74ALS166D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS166 SN74ALS166DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 G166 SN74ALS166DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS166 SN74ALS166N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74ALS166N SN74ALS166NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS166 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of