SN74ALS29821NT


  
 
  



SDAS145B − JANUARY 1986 − REVISED JANUARY 1995 • • • • • • SN54ALS29821 . . . JT PACKAGE SN74ALS29821 . . . DW OR NT PACKAGE (TOP VIEW) Functionally Equivalent to AMD’s AM29821 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State Buffered Control Inputs Reduce dc Loading Effects Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK These 10-bit edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input. A buffered output-enable (OE) input can place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS29821 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74ALS29821 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L L X Q0 H X X Z Copyright  1995, Texas Instruments Incorporated   !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/ #".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&' '&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/ • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 

  
 
  



SDAS145B − JANUARY 1986 − REVISED JANUARY 1995 logic symbol† OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 EN 13 2 C1 23 1D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE CLK 1 13 C1 1D 2 1D 23 1Q To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54ALS29821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74ALS29821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 

  
 
  



SDAS145B − JANUARY 1986 − REVISED JANUARY 1995 recommended operating conditions SN54ALS29821 SN74ALS29821 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current −24 −24 mA IOL tw Low-level output current 48 48 mA Pulse duration, CLK high or low 7 7 ns tsu th Setup time, data before CLK↑ 4 4 ns TA Operating free-air temperature High-level input voltage 2 Hold time, data after CLK↑ 2 2 V 2 −55 125 V ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK SN54ALS29821 TYP† MAX TEST CONDITIONS VCC = 4.75 V, VOH VCC = 4.75 V VOL IOZH VCC = 4.75 V, VCC = 5.25 V, IOZL II VCC = 5.25 V, VCC = 5.25 V, IIH IIL VCC = 5.25 V, VCC = 5.25 V, IOS‡ ICC VCC = 5.25 V, VCC = 5.25 V, MIN II = − 18 mA IOH = − 15 mA SN74ALS29821 TYP† MAX MIN −1.2 IOH = − 24 mA IOL = 48 mA 3.3 2.4 3.3 2 3.1 2 3.1 0.35 VO = 2.4 V VO = 0.4 V VI = 5.5 V VI = 2.7 V VI = 0.4 V VO = 0 −1.2 2.4 0.5 0.35 Outputs open V 0.5 V 20 µA −50 −20 µA 0.1 0.1 mA 20 20 µA −250 80 V 50 −0.5 −75 UNIT 115 −75 80 −0.2 mA −250 mA 115 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 

  
 
  



SDAS145B − JANUARY 1986 − REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS tPLH tPHL CLK Any Q CL = 50 pF tPLH tPHL CLK Any Q CL = 300 pF tPZH tPZL OE Any Q CL = 50 pF tPZH tPZL OE Any Q CL = 300 pF tPHZ tPLZ OE Any Q CL = 50 pF tPHZ tPLZ OE Any Q CL = 5 pF VCC = MIN to MAX†, TA = MIN to MAX† SN54ALS29821 SN74ALS29821 MIN MAX MIN MAX 2 11.5 2 10 2 11.5 2 10 2 21 16 2 21 16 1 17 14 1 17 14 1 25 20 1 29.5 23 1 16 14 1 14 12 1 12 9 1 11 9 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT ns ns ns ns ns ns 

  
 
  



SDAS145B − JANUARY 1986 − REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION Test Point VCC SWITCH POSITION TABLE S1 From Output Under Test RL = 180 Ω All Diodes 1N916 or 1N3064 R1 1 kΩ CL (see Note A) S2 TEST S1 S2 tPLH tPHL tPZH tPZL tPHZ tPLZ Closed Closed Open Closed Closed Closed Closed Closed Closed Open Closed Closed LOAD CIRCUIT High-Level Pulse 3V 1.5 V Timing Input 3V 1.5 V 0 0 tw th tsu 1.5 V 3V 3V Low-Level Pulse 1.5 V 1.5 V Data Input 0 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control 1.5 V 1.5 V 0 tPZL tPLZ ≈ 4.5 V 3V Input 1.5 V 1.5 V Waveform 1 (see Note B) 0 tPHL tPLH 1.5 V Out-of-Phase Output tPHZ 1.5 V VOL VOH Waveform 2 (see Note B) VOH 1.5 V 0.5 V tPZH tPLH tPHL ≈ 1.5 V VOL VOH In-Phase Output 1.5 V 1.5 V 1.5 V 0.5 V ≈ 1.5 V ≈0 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 5962-9061601LA ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN74ALS29821DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SNJ54ALS29821JT ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9061601LA SNJ54ALS29821J T ALS29821 5962-9061601LA SNJ54ALS29821J T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of