SN74ALS533ADWRG4

SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 • • • • • • DW OR N PACKAGE (TOP VIEW) Eight Latches in a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading Buffered Control Inputs pnp Inputs Reduce dc Loading on Data Lines Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE These 8-bit D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALS533A and SN74AS533A are functionally equivalent to the SN74ALS373A and SN74AS373, except for having inverted outputs. A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. The SN74ALS533A and SN74AS533A are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H L L H L H L L X Q0 H X X Z Copyright  1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 logic symbol† 1 OE LE 1D 2D 3D 4D 5D 6D 7D 8D 11 3 4 logic diagram (positive logic) OE EN LE C1 1D 1 2 5 7 6 8 9 13 12 14 15 17 16 18 1 19 11 C1 1Q 1D 3 2 1Q 1D 2Q 3Q 4Q C1 2D 4 5Q C1 8Q 3D † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 12 5Q 13 1D 14 17 18 15 6Q 1D 16 7Q 1D C1 8D 4Q 1D C1 7D 9 8 C1 6D 3Q 1D C1 5D 6 7 C1 4D 2Q 1D 6Q 7Q 5 19 8Q 1D absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN74ALS533A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 recommended operating conditions SN74ALS533A MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage High-level output current – 2.6 mA IOL tw Low-level output current 24 mA Pulse duration, LE high 15 ns tsu th Setup time, data before LE↓ 15 ns Hold time, data after LE↓ 7 ns TA Operating free-air temperature 0 High-level input voltage 2 V V 0.8 70 V °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VCC = 4.5 V, IOH = – 2.6 mA IOL = 12 mA VOL VCC = 4 4.5 5V IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, II IIH VCC = 5.5 V, VCC = 5.5 V, IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, ICC VCC = 5.5 V SN74ALS533A TYP† MAX MIN – 1.5 VCC – 2 2.4 IOL = 24 mA VO = 2.7 V 0.25 0.4 0.35 0.5 20 VI = 2.7 V VI = 0.4 V VO = 2.25 V Outputs high Outputs low Outputs disabled – 30 V V 3.2 VO = 0.4 V VI = 7 V UNIT V µA – 20 µA 0.1 mA 20 µA – 0.1 mA – 112 mA 10 17 17 26 18.5 28 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† UNIT SN74ALS533A tPLH tPHL D Q tPLH tPHL LE An Q Any tPZH tPZL OE An Q Any tPHZ tPLZ OE Any Q MIN MAX 4 19 4 13 5 23 4 18 1 17 4 18 2 10 2 16 ns ns ns ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN74AS533A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN74AS533A MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage IOL tw Low-level output current Pulse duration, LE high 2 ns tsu th Setup time, data before LE↓ 2 ns Hold time, data after LE↓ 3 TA Operating free-air temperature 0 4 High-level input voltage 2 High-level output current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 0.8 V – 15 mA 48 mA ns 70 °C SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IO‡ ICC SN74AS533A TYP† MAX TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VCC = 4.5 V, VCC = 4.5 V, IOH = – 15 mA IOL = 48 mA VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VCC = 5.5 V – 1.5 VCC – 2 2.4 0.34 – 0.02 V V 3.3 – 30 UNIT 0.5 V 50 µA – 50 µA 0.1 mA 20 µA – 0.5 mA – 112 mA Outputs high 62 100 Outputs low 64 100 Outputs disabled 71 110 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE An Q Any tPZH tPZL OE An Q Any tPHZ tPLZ OE Any Q VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ SN74AS533A MIN MAX 4 7.5 4 7 5 9 4 8 2 6.5 4 9.5 2 6.5 3 7 UNIT ns ns ns ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALS533A, SN74AS533A OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SDAS270 – DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74ALS533ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS533A SN74ALS533AN ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN74ALS533AN SN74ALS533ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS533A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of