SN74ALS990NG4

SN74ALS990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH SDAS027B – APRIL 1984 – REVISED JANUARY 1995 • • • • DW OR N PACKAGE (TOP VIEW) 3-State I/O-Type Read-Back Inputs Bus-Structured Pinout True Logic Outputs Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs OERB 1D 2D 3D 4D 5D 6D 7D 8D GND description This 8-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE The eight latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. Read back is provided through the output-enable (OERB) input. When OERB is taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. When OERB is taken high, the output of the data latches is isolated from the D inputs. OERB does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict. The SN74ALS990 is characterized for operation from 0°C to 70°C. logic symbol† 1 OERB LE 1D 11 2 EN2 C1 1D 19 2 2D 3D 4D 5D 6D 7D 8D 3 18 4 17 5 16 6 15 7 14 8 13 9 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH SDAS027B – APRIL 1984 – REVISED JANUARY 1995 logic diagram (positive logic) OERB LE 1D 1 11 2 1D 19 1Q C1 To Seven Other Channels timing diagram Data Bus Input Data tsu Read Back Input Data th LE tsu† ten tdis OERB tpd tpd Q † This setup time ensures that the read-back circuit will not create a conflict on the input data bus. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (OERB and LE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to D inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH SDAS027B – APRIL 1984 – REVISED JANUARY 1995 recommended operating conditions VCC VIH Supply voltage VIL Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level tw Pulse duration, LE high High-level input voltage MIN NOM MAX 4.5 5 5.5 2 Q – 2.6 D – 0.4 Q 24 D 8 10 10 Data before OERB↓ 10 tsu Setup time th TA Hold time, data after LE↓ 5 Operating free-air temperature 0 V V 0.8 Data before LE↓ UNIT V mA mA ns ns ns 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS All outputs VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA Q VCC = 4.5 V, D VCC = 4 4.5 5V IOH = – 2.6 mA IOL = 4 mA VOL Q II OERB, LE D inputs VCC = 4 4.5 5V VCC = 5 5.5 5V UNIT – 1.2 V VCC – 2 2.4 V 3.2 IOL = 8 mA IOL = 12 mA 0.35 0.5 0.25 0.4 IOL = 24 mA VI = 5.5 V 0.35 0.5 0.1 VI = 7 V VCC = 5 5.5 5V V, VI = 2 2.7 7V IIL OERB, LE D inputs‡ 5V VCC = 5 5.5 V, 4V VI = 0 0.4 VCC = 5.5 V, VO = 2.25 V Outputs high VCC = 5.5 V, OERB high MAX 0.4 OERB, LE D inputs‡ ICC TYP† 0.25 IIH IO§ MIN Outputs low 0.1 20 20 – 0.1 – 0.1 – 30 –112 27 50 40 70 V mA µA mA mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALS990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH SDAS027B – APRIL 1984 – REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM ((INPUT)) TO (OUTPUT) ( ) tPLH tPHL D Q tPLH tPHL LE Q OERB D ten‡ tdis§ VCC = 4.5 V to 5.5 V, CL = 50 pF, TA = MIN to MAX† MIN MAX 4 17 5 24 6 26 8 26 4 21 ns 19 ns 4 OERB D † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ ten = tPZH or tPZL § tdis = tPHZ or tPLZ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns SN74ALS990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCH SDAS027B – APRIL 1984 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V S1 1 kΩ Test Point From Output Under Test CL (see Note A) CL (see Note A) 500 Ω LOAD CIRCUIT FOR Q OUTPUTS 1 kΩ LOAD CIRCUIT FOR D OUTPUTS 3.5 V Timing Input Test Point From Output Under Test 1.3 V 3.5 V High-Level Pulse 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.3 V 0.3 V 3.5 V Output Control (low-level enabling) 1.3 V tPHL tPLH VOH 1.3 V 1.3 V tPHL Out-of-Phase Output (see Note B) Waveform 1 S1 Closed (see Note C) VOL tPLH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V 0.3 V tPZL 1.3 V tPLZ 0.3 V In-Phase Output 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V 1.3 V Input 3.5 V Low-Level Pulse [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note C) VOL 0.3 V VOH 1.3 V 0.3 V [0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. When measuring propagation delay times of 3-state outputs, switch S1 is open. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74ALS990DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS990 Samples SN74ALS990DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS990 Samples SN74ALS990N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN74ALS990N Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of