SN74ALVC7803-25DLR

SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 • • • • • • • • • • • • Operates at 3-V to 3.6-V VCC Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized to Independent System Clocks Low-Power Advanced CMOS Technology Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag Bidirectional Configuration and Width Expansion Without Additional Logic Input-Ready Flag Synchronized to Write Clock Output-Ready Flag Synchronized to Read Clock Fast Access Times of 13 ns With a 50-pF Load and All Data Outputs Switching Simultaneously Data Rates From 0 to 50 MHz Pin Compatible With SN74ACT7803 Packaged in Shrink Small-Outline 300-mil Package (DL) Using 25-mil Center-to-Center Lead Spacing description The SN74ALVC7803 FIFO is suited for buffering asynchronous data paths at 50-MHz clock rates and 13-ns access times and is designed for 3-V to 3.6-V VCC operation. The 56-pin shrink smalloutline (DL) package offers greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured for bidirectional data buffering without additional logic. DL PACKAGE (TOP VIEW) RESET D17 D16 D15 D14 D13 D12 D11 D10 VCC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 HF PEN AF/AE WRTCLK WRTEN2 WRTEN1 IR 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OE1 Q17 Q16 Q15 GND Q14 VCC Q13 Q12 Q11 Q10 Q9 GND Q8 Q7 Q6 Q5 VCC Q4 Q3 Q2 GND Q1 Q0 RDCLK RDEN OE2 OR The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full /almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 logic symbol† 1 RESET WRTCLK WRTEN1 Φ FIFO 512 × 18 RESET 25 WRTCLK 27 & WRTEN 26 In RDY WRTEN2 RDCLK 32 Half Full RDCLK Almost Full / Empty 56 OE1 & 30 Out RDY EN1 28 22 24 29 IR HF AF/AE OR OE2 & RDEN 31 RDEN PEN D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 23 21 Program Enable 0 0 34 19 36 18 37 17 38 16 40 15 41 14 42 12 43 11 45 Data Data 1 9 46 8 47 7 48 6 49 5 51 4 53 3 54 2 55 17 17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 33 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 functional block diagram OE1 OE2 Output Control D0 – D17 RDCLK RDEN SynchronousRead Control RAM Read Pointer 512 × 18 WRTCLK WRTEN1 WRTEN2 SynchronousWrite Control Write Pointer Register RESET StatusFlag Logic Reset Logic Q0 – Q17 OR IR HF PEN AF/AE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 Terminal Functions TERMINAL NAME 4 NO. I/O DESCRIPTION AF/AE 24 O Almost-full/almost-empty flag. Depth offset values can be programmed for AF/AE, or the default value of 64 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or less words or (512 minus Y) or more words. AF/AE is high after reset. D0 – D17 21 – 14, 12 – 11, 9–2 I 18-bit data input port HF 22 O Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset. IR 28 O Input ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full and writes are disabled. IR is low during reset and goes high on the second low-to-high transition of WRTCLK after reset. OE1, OE2 56, 30 I Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO on a low-to-high transition of RDCLK. When either OE1 or OE2 is high, reads are disabled and the data outputs are in the high-impedance state. OR 29 O Output ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty and reads are disabled. Ready data is present on Q0 – Q17 when OR is high. OR is low during reset and goes high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory. PEN 23 I Program enable. After reset and before the first word is written to the FIFO, the binary value on D0 – D7 is latched as an AF/AE offset value when PEN is low and WRTCLK is high. Q0 – Q17 33 – 34, 36 – 38, 40 – 43, 45 – 49, 51, 53 – 55 O 18-bit data output port. After the first valid write to empty memory, the first word is output on Q0 – Q17 on the third rising edge of RDCLK. OR is also asserted high at this time to indicate ready data. When OR is low, the last word read from the FIFO is present on Q0 – Q17. RDCLK 32 I Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A low-to-high transition of RDCLK reads data from memory when OE1, OE2, and RDEN are low and OR is high. OR is synchronous to the low-to-high transition of RDCLK. RDEN 31 I Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on the low-to-high transition of RDCLK. RESET 1 I Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. WRTCLK 25 I Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTEN1 is high, and IR is high. IR is synchronous to the low-to-high transition of WRTCLK. WRTEN1, WRTEN2 27, 26 I Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO on a low-to-high transition of WRTCLK. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 RESET PEN 1 WRTCLK 2 3 4 1 2 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ WRTEN1 Don’t Care WRTEN2 Don’t Care Don’t Care D0 – D17 1 RDCLK 2 3 4 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ OE1 Don’t Care RDEN Don’t Care OE2 Don’t Care Q0 – Q17 Invalid OR Don’t Care AF/AE Don’t Care HF Don’t Care IR Don’t Care Define the AF/AE Flag Using the Default Value of X = Y = 64 Figure 1. Reset Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 RESET 1 0 PEN 1 0 WRTCLK 1 0 WRTEN1 WRTEN2 D0 – D17 RDCLK ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ W1 W2 W3 W4 1 2 3 W(X+2) A B C 1 0 OE1 RDEN OE2 Q0 – Q17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Invalid W1 OR AF/AE HF IR DATA WORD NUMBER FOR FLAG TRANSITIONS TRANSITION WORD DEVICE SN74ALVC7803 A B C W257 W((513 – Y) W513 Figure 2. FIFO Write 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 0 1 0 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 RESET 1 0 PEN 1 0 2 1 WRTCLK WRTEN1 WRTEN2 D0 – D17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 0 W513 RDCLK 1 0 OE1 RDEN OE2 Q0 – Q17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ W1 W2 W3 W(Y+1) W(Y+2) A B C D E F OR AF/AE HF IR DATA WORD NUMBERS FOR FLAG TRANSITIONS DEVICE SN74ALVC7803 TRANSITION WORD A B C D E F W257 W258 W(512 – X) W(513 – X) W512 W513 Figure 3. FIFO Read POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 offset values for AF/AE The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the offsets are not programmed, the default values of X = Y = 64 are used. The AF/AE flag is high when the FIFO contains X or less words or (512 minus Y) or more words. Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR is high. On the following low-to-high transition of WRTCLK, the binary value on D0 – D7 is stored as the almost empty offset value (X) and the almost full offset value (Y). Holding PEN low for another low-to-high transition of WRTCLK reprograms Y to the binary value on D0 – D7 at the time of the second WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are disabled regardless of the state of WRTEN1 and WRTEN2. A maximum value of 255 can be programmed for either X or Y (see Figure 4). To use the default values of X = Y = 64, PEN must be held high. RESET WRTCLK PEN D0 – D7 3 4 ÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉ X and Y ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ Y IR WRTEN1 WRTEN2 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Figure 4. Programming X and Y Separately absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V 50 mA Input clamp current, IIK ( VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK ( VO < 0 or VO > VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO ( VO = 0 to VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C * " " " † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings can be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 recommended operating conditions " VCC = 3.3 V 0.3 V MIN MAX VIH VIL High-level input voltage IOH High-level g output current,, Q outputs, flags IOL Low-level output current,, Q outputs, flags fclock Clock frequency tw tsu th 2 Low-level input voltage Pulse duration Setup time Hold time " VCC = 3.3 V 0.3 V MIN MAX 2 " VCC = 3.3 V 0.3 V MIN MAX 2 UNIT V 0.8 0.8 0.8 VCC = 3 V –8 –8 –8 VCC = 3 V 16 16 16 V mA 50 40 25 D0 – D17 high or low 9 10 14 WRTCLK high or low 7 8 12 RDCLK high or low 7 8 12 PEN low 9 9 12 WRTEN1 high, g , WRTEN2 low 8 8 12 OE1, OE2 low 9 9 12 RDEN low 8 8 12 D0 – D17 before WRTCLK↑ 5 5 5 WRTEN1, WRTEN2 before WRTCLK↑ 5 5 5 OE1, OE2 before RDCLK↑ 5 6 6 RDEN before RDCLK↑ 5 5 7 Reset: RESET low before first WRTCLK↑ and RDCLK↑† 6 6 6 PEN before WRTCLK↑ 6 6 6 D0 – D17 after WRTCLK↑ 0 0 0 WRTEN1, WRTEN2 after WRTCLK↑ 0 0 0 OE1, OE2, RDEN after RDCLK↑ 0 0 0 Reset: RESET low after fourth WRTCLK↑ and RDCLK↑† 2 2 2 PEN low after WRTCLK↑ 2 2 2 TA Operating free-air temperature † To permit the clock pulse to be utilized for reset purposes MHz ns ns ns 0 POST OFFICE BOX 655303 70 • DALLAS, TEXAS 75265 0 70 0 70 °C 9 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS† PARAMETER VIK MIN VCC = 3 V, VCC = MIN to MAX, IIK = – 18 mA IOH = –100 µA VCC = 3 V, VCC = MIN to MAX, IOH = – 8 mA IOL = 100 µA VCC = 3 V, VCC = 3 V, IOL = 8 mA IOL = 16 mA II IOZ VCC = 3.6 V, VCC = 3.6 V, VI =VCC or GND VO =VCC or GND ICC VI = VCC or 0, VCC = 3.6 V, One input at VCC – 0.6 V IO = 0 Other inputs at VCC or GND, VCC = 3.3 V, VCC = 3.3 V, VI = VCC or GND, f = 1 MHz VO = VCC or GND, f = 1 MHz Flags VOH Q outputs Flags, Q outputs VOL Flags Q outputs ∆ICC§ Ci TYP‡ MAX UNIT –1.2 V VCC – 0.2 2.4 V 0.2 0.4 V 0.55 ±5 µA ±10 µA 40 µA 500 µA 2.5 pF Co 5.5 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. § This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 7) PARAMETER FROM (OUTPUT) TO (INPUT) fmax WRTCLK or RDCLK tpd tpd¶ RDCLK↑ " VCC = 3.3 V 0.3 V MIN MAX 50 Any Q " VCC = 3.3 V 0.3 V MIN MAX " VCC = 3.3 V 0.3 V MIN MAX 40 25 UNIT MHz 4 13 4 15 4 20 ns tpd tpd WRTCLK↑ IR 3 11 3 13 3 15 ns RDCLK↑ OR 3 11 3 13 3 15 ns tpd tpd WRTCLK↑ AF/AE 7 19 7 21 7 23 ns RDCLK↑ AF/AE 7 19 7 21 7 23 ns tPLH tPHL WRTCLK↑ 7 17 7 19 7 21 7 18 7 20 7 22 HF RDCLK↑ tPLH tPHL RESET low lo ten tdis OE1 OE2 OE1, AF/AE 2 11 2 13 2 15 HF 2 12 2 14 2 16 2 11 2 11 2 14 2 11 2 14 2 14 Any Q ns ns ns ¶ This parameter is measured with a 50-pF load (see Figure 7). operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd 10 Power dissipation capacitance TEST CONDITIONS Outputs enabled POST OFFICE BOX 655303 CL = 50 pF, • DALLAS, TEXAS 75265 f = 5 MHz TYP UNIT 53 pF SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 APPLICATION INFORMATION SN74ALVC78xx WRTCLK RDCLK CLOCK A W/ RA WRTEN1 OE1 CSA WRTEN2 RDEN CLOCK B W/ RB CSB OE2 18 D0 – D17 Q0 – Q17 B0 – B17 SN74ALVC78xx RDCLK WRTCLK OE1 WRTEN1 RDEN WRTEN2 OE2 18 A0 – A17 Q0 – Q17 D0 – D17 Figure 5. Bidirectional Configuration SN74ALVC78xx WRTCLK RDCLK WRTCLK WRTEN1 WRTEN1 RDEN WRTEN2 WRTEN2 OE1 IR RDCLK OE1 OR OE2 OE2 36 D0 – D35 D0 – D17 Q0 – Q17 OR IR SN74ALVC78xx WRTCLK RDCLK WRTEN1 RDEN WRTEN2 OE1 IR OR OE2 36 D0 – D17 Figure 6. Word-Width Expansion: 512 POST OFFICE BOX 655303 Q0 – Q17 36 Bit , 256 • DALLAS, TEXAS 75265 Q0 – Q35 36 Bit, and 64 36 Bit 11 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 140 fdata = 1/2 fclock TA = 75°C CL = 0 pF I CCf – Supply Current – mA 120 VCC = 3.6 V 100 VCC = 3.3 V 80 60 VCC = 3 V 40 20 0 0 10 20 30 40 50 60 70 80 90 fclock – Clock Frequency – MHz Figure 7 calculating power dissipation With ICCf taken from Figure 7, the dynamic power (Pd), based on all data outputs changing states on each read, can be calculated by using: Pd = VCC × [ICC(f) + (N × ∆ICC × dc)] + ∑(CL × VCC2 × fo) A more accurate total power (PT) can be calculated if quiescent power (Pq) is also taken into consideration. Quiescent power (Pq) can be calculated using: Pq = VCC × [ICCI + (N × ∆ICC × dc)] Total power would be: PT = Pd + Pq The above equations provide worst-case power calculations. Where: N ∆ICC dc CL fo ICCI pF ICCf 12 = = = = = = number of inputs driven by TTL levels increase in power supply current for each input at a TTL high level duty cycle of inputs at a TTL high level of 3.4 V output capacitance load switching frequency of an output idle current, supply current when FIFO is idle ≈ pF × fclock = 0.2 × fclock (current is due to free-running clocks) = power factor (the slope of idle current versus clock frequency). = active current, supply current when FIFO is transferring data POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SDAS274 – JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω LOAD CIRCUIT FOR OUTPUTS tw 3V Input 3V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 1.5 V 1.5 V 0V tPLH tPHL Output Waveform 2 S1 at GND (see Note C) VOH 1.5 V tPLZ 3V Output Waveform 1 S1 at 6 V (see Note C) 1.5 V 1.5 V VOL 1.5 V 0V tPZL 3V 1.5 V 3V Output Control (low-level enabling) 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.5 V 1.5 V tsu Input (see Note B) 1.5 V 1.5 V VOL + 0.3 V VOL tPHZ tPZH VOH 1.5 V VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. v v v 3-STATE OUTPUTS (ANY Q) PARAMETER R1, R2 CL† ten tPZH tPZL 500 Ω 50 pF tdi dis tPHZ tPLZ 500 Ω 50 pF tpd tPLH / tPHL 500 Ω 50 pF S1 GND 6V GND 6V Open † Includes probe and test-fixture capacitance Figure 8. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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