SN74ALVCH162334DL

www.ti.com FEATURES • • Member of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process Output Port Has Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 DGG, DGV, OR DL PACKAGE (TOP VIEW) 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 CLK A1 A2 GND A3 A4 VCC A5 A6 GND A7 A8 A9 A10 GND A11 A12 VCC A13 A14 GND A15 A16 LE DESCRIPTION OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6 GND Y7 Y8 Y9 Y10 GND Y11 Y12 VCC Y13 Y14 GND Y15 Y16 NC This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. NC − No internal connection • • • • • • NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162334 is characterized for operation from -40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2004, Texas Instruments Incorporated SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 FUNCTION TABLE INPUTS (1) OE LE CLK A OUTPUT Y H X X X Z L L X L L L L X H H L H ↑ L L L H ↑ H H L H L or H X Y0 (1) Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high LOGIC DIAGRAM (POSITIVE LOGIC) 1 OE 48 CLK LE 25 47 A1 1D C1 CLK To 15 Other Channels 2 2 Y1 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.5 IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IO Continuous output current Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg (1) (2) (3) (4) mA -50 mA ±50 mA ±100 mA DGG package 89 DGV package 93 DL package 94 Storage temperature range -65 V -50 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VIH High-level input voltage VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current 1.7 VCC = 2.7 V to 3.6 V 2 Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 V 0 VCC V 0 VCC V VCC = 1.65 V -2 VCC = 2.3 V -6 VCC = 2.7 V -8 mA -12 VCC = 1.65 V 2 VCC = 2.3 V 6 VCC = 2.7 V 8 VCC = 3 V (1) V VCC = 2.3 V to 2.7 V VCC = 3 V IOL V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V VIL UNIT mA 12 -40 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA VOH 1.65 V to 3.6 V II(hold) VCC - 0.2 1.65 V 1.2 IOH = -4 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = -8 mA 2.7 V 2 IOH = -12 mA 3V 2 IOL = 100 µA V 1.65 V to 3.6 V 0.2 IOL = 2 mA 1.65 V 0.45 IOL = 4 mA 2.3 V 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA 2.7 V 0.6 IOL = 12 mA 3V 0.8 IOL = 6 mA II MIN TYP (1) MAX UNIT IOH = -2 mA IOH = -6 mA VOL VCC ±5 VI = VCC or GND 3.6 V VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V -25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V -45 VI = 0.8 V 3V 75 3V -75 VI = 2 V V µA µA VI = 0 to 3.6 V (2) 3.6 V ±500 IOZ VO = VCC or GND 3.6 V ±10 µA ICC VI = VCC or GND, IO = 0 3.6 V 40 µA One input at VCC - 0.6 V, Other inputs at VCC or GND 750 µA ∆ICC Ci Co (1) (2) 4 Control inputs Data inputs Outputs 3 V to 3.6 V VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V 5.5 6 8 All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. pF pF SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) VCC = 1.8 V MIN MAX fclock tw tsu th (1) Setup time Hold time MIN MAX (1) Clock frequency Pulse duration VCC = 2.5 V ± 0.2 V VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN 150 150 MHz LE low (1) 3.3 3.3 3.3 CLK high or low (1) 3.3 3.3 3.3 Data before CLK↑ (1) 1.4 1.7 1.5 CLK high (1) 1.2 1.6 1.3 CLK low (1) 1.4 1.5 1.2 (1) 0.9 0.8 0.9 (1) 1.2 1.1 1.1 Data before LE↑ Data after CLK↑ Data after LE↑ CLK high or low UNIT MAX ns ns ns This information was not available at the time of publication. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) PARAMETER FROM (INPUT) VCC = 1.8 V TO (OUTPUT) MIN (1) fmax A tpd LE Y CLK (1) TYP VCC = 2.5 V ± 0.2 V VCC = 2.7 V MIN MAX MIN 150 150 MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz (1) 1 3.9 4.5 1.1 3.9 (1) 1 5 6 1.3 5 (1) ns 1 4.9 5.4 1 4.9 ten OE Y (1) 1 5.4 6.4 1.1 5.4 ns tdis OE Y (1) 1 5 5.1 1.7 5 ns This information was not available at the time of publication. OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd Power dissipation capacitance (1) TEST CONDITIONS Outputs enabled Outputs disabled CL = 0, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 32 37 (1) 7 11.5 UNIT pF This information was not available at the time of publication. 5 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 1 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 Ω S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 7 SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Output Control (low-level enabling) 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V Output Waveform 2 S1 at GND (see Note B) tPHZ 1.5 V VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 8 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74ALVCH162334DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162334 SN74ALVCH162334GR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162334 SN74ALVCH162334VR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VH2334 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of