www.ti.com
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
FEATURES
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
B-Port Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Option Includes Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR.
DESCRIPTION
This 18-bit universal bus transceiver is designed for
1.65-V to 3.6-V VCC operation.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA) and clock-enable
(CLKENAB and CLKENBA) inputs. For the A-to-B
data flow, the data flows through a single register.
The B-to-A data can flow through a four-stage
pipeline register path, or through a single register
path, depending on the state of the select (SEL)
input.
DGG OR DL PACKAGE
(TOP VIEW)
CLKENAB
OEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
CLKENBA
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
SEL
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLK1BA
CLK2BA
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the
appropriate CLKEN inputs are low. The A-to-B data transfer is synchronized to the CLKAB input, and B-to-A data
transfer is synchronized with the CLK1BA and CLK2BA inputs.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162525 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
FUNCTION TABLES
XXX
A-TO-B STORAGE
(OEAB = L)
INPUTS
(1)
CLKENAB
CLKAB
A
OUTPUT
B
H
X
X
B0 (1)
L
↑
L
L
L
↑
H
H
Output level before the indicated steady-state input conditions were
established
B-TO-A STORAGE
(OEBA = L)
INPUTS
(1)
(2)
2
CLKENBA
CLK2BA
CLK1BA
SEL
B
OUTPUT
A
H
X
X
X
X
A0 (1)
L
↑
X
H
L
L
L
↑
X
H
H
H
L
↑
↑
L
L
L (2)
L
↑
↑
L
H
H (2)
Output level before the indicated steady-state input conditions were established
Three CLK1BA edges and one CLK2BA edge are needed to propagate data from B to A when SEL is
low.
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
CLKAB
CLK1BA
55
30
29
CLK2BA
CLKENBA
CLKENAB
OEAB
OEBA
SEL
28
1
2
27
56
1 of 18 Channels
G1
CE
3
A1
C1
1D
1
1
CE
C1
1D
CE
C1
1D
CE
C1
1D
54
B1
CE
C1
1D
3
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
MIN
MAX
–0.5
4.6
Except I/O ports (2)
–0.5
4.6
I/O ports (2) (3)
–0.5
VCC + 0.5
–0.5
VCC + 0.5
UNIT
V
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
4
DGG package
81
DL package
74
–65
150
V
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
www.ti.com
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
High-level output current (A port)
IOH
High-level output current (B port)
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
IOL
Low-level output current (B port)
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0
VCC
V
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–12
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
–2
VCC = 2.3 V
–6
VCC = 2.7 V
mA
–8
–12
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
VCC = 1.65 V
2
VCC = 2.3 V
6
VCC = 2.7 V
mA
8
VCC = 3 V
∆t/∆v
V
0.35 × VCC
VCC = 3 V
Low-level output current (A port)
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
12
–40
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
1.65 V
IOH = –6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2
IOH = –24 mA
IOH = –100 µA
A port
B port
II
1.65 V
1.2
IOH = –4 mA
2.3 V
1.9
2.3 V
1.7
3V
2.4
IOH = –6 mA
IOH = –8 mA
2.7 V
2
IOH = –12 mA
3V
2
IOL = 100 µA
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
IOL = 24 mA
3V
0.55
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 2 mA
1.65 V
0.45
IOL = 4 mA
2.3 V
0.4
2.3 V
0.55
IOL = 6 mA
3V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3V
0.8
±5
3.6 V
VI = 0.58 V
1.65 V
VI = 1.07 V
VI = 0.7 V
2.3 V
VI = 1.7 V
VI = 0.8 V
3V
VI = 2 V
V (2)
IOZ (3)
VO = VCC or GND
ICC
VI = VCC or GND,
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
V
IOL = 4 mA
VI = 0 to 3.6
UNIT
1.2
IOH = –2 mA
VI = VCC or GND
II(hold)
MAX
1.65 V to 3.6 V VCC – 0.2
IOL = 12 mA
VOL
TYP (1)
1.65 V to 3.6 V VCC – 0.2
IOH = –12 mA
B port
MIN
IOH = –4 mA
A port
VOH
VCC
V
µA
25
–25
45
µA
–45
75
–75
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
750
µA
3 V to 3.6 V
Ci
Control inputs
VI = VCC or GND
3.3 V
3
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
7
pF
(1)
(2)
(3)
6
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 1.8 V
MIN
Clock frequency
tw
Pulse duration, CLK high or low
th
(1)
Setup time
Hold time
MIN
MAX
(1)
fclock
tsu
MAX
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
MIN
MAX
120
125
150
(1)
3.2
3.2
3
A data before CLKAB↑
(1)
1.3
1.3
1.3
B data before CLK2BA↑
(1)
2.1
1.8
1.7
B data before CLK1BA↑
(1)
1.3
1.2
1.1
SEL before CLK2BA↑
(1)
3.3
3.3
3.3
CLKENAB before CLKAB↑
(1)
2.1
1.9
1.6
CLKENBA before CLK1BA↑
(1)
2.7
2.5
2.1
CLKENBA before CLK2BA↑
(1)
2.7
2.5
2.2
A data after CLKAB↑
(1)
0.7
0.4
0.9
B data after CLK2BA↑
(1)
0.4
0
0.6
B data after CLK1BA↑
(1)
0.8
0.4
1
SEL after CLK2BA↑
(1)
0
0
0.1
CLKENAB after CLKAB↑
(1)
0.1
0.3
0.3
CLKENBA after CLK1BA↑
(1)
0
0
0.1
CLKENBA after CLK2BA↑
(1)
0
0
0
UNIT
MAX
MHz
ns
ns
ns
This information was not available at the time of publication.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
TO
(OUTPUT)
MIN
ten
tdis
(1)
MAX
(1)
fmax
tpd
VCC = 2.5 V
± 0.2 V
MIN
VCC = 2.7 V
MAX
120
VCC = 3.3 V
± 0.3 V
MIN MAX
MIN
125
150
UNIT
MAX
MHz
CLKAB
B
(1)
1
5.5
5.4
1
4.7
CLK2BA
A
(1)
1
4.5
4.4
1
4.2
OEBA
A
(1)
1
6.1
6.1
1
5.1
OEAB
B
(1)
1
6.7
6.8
1
5.7
OEBA
A
(1)
1
6.3
5.4
1
4.9
OEAB
B
(1)
1
6.3
5.4
1
4.9
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
160
160
(1)
160
160
ns
ns
ns
This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd Power dissipation capacitance
(1)
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
f = 10 MHz
UNIT
pF
This information was not available at the time of publication.
7
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
1 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
8
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
500 Ω
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
9
SN74ALVCH162525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES058H – NOVEMBER 1995 – REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
From Output
Under Test
6V
Open
S1
500 Ω
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
Input
1.5 V
0V
1.5 V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VOH
1.5 V
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
10
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ALVCH162525DLG4
ACTIVE
SSOP
DL
56
74ALVCH162525GRE4
ACTIVE
TSSOP
DGG
74ALVCH162525GRG4
ACTIVE
TSSOP
SN74ALVCH162525DGGR
OBSOLETE
SN74ALVCH162525DL
ACTIVE
SN74ALVCH162525GR
ACTIVE
20
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TSSOP
DGG
56
SSOP
DL
56
TSSOP
DGG
56
TBD
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74ALVCH162525GR
Package Package Pins
Type Drawing
TSSOP
DGG
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALVCH162525GR
TSSOP
DGG
56
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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